Specification Update
Page 2
... rights reserved. *Other names and brands may be claimed as errata which processors support HT Technology, visit http://www.intel.com/info/hyperthreading 64-bit Intel® Xeon® processors with Intel®64 requires a computer system with all operating systems. Consult your PC manufacturer. Current...PROPERTY RIGHT. Performance will vary depending on Intel® Core™ i5-750. Check with your product order. INFORMATION Legal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. Intel®64-enabled OS, BIOS, device drivers and ...
... rights reserved. *Other names and brands may be claimed as errata which processors support HT Technology, visit http://www.intel.com/info/hyperthreading 64-bit Intel® Xeon® processors with Intel®64 requires a computer system with all operating systems. Consult your PC manufacturer. Current...PROPERTY RIGHT. Performance will vary depending on Intel® Core™ i5-750. Check with your product order. INFORMATION Legal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. Intel®64-enabled OS, BIOS, device drivers and ...
Specification Update
Page 5
...core speed, L2 cache size, package type, etc. Hardware and software designed to deviate from published specifications. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 Related Documents Document Title Document Number/ Location AP-485, Intel® Processor Identification and the CPUID Instruction 241618 Intel® 64... S-Spec number. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for that was not previously published....
...core speed, L2 cache size, package type, etc. Hardware and software designed to deviate from published specifications. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 Related Documents Document Title Document Number/ Location AP-485, Intel® Processor Identification and the CPUID Instruction 241618 Intel® 64... S-Spec number. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for that was not previously published....
Specification Update
Page 7
This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 This erratum has been ... in Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP ...
This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 This erratum has been ... in Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP ...
Specification Update
Page 8
...® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor MP...
...® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor MP...
Specification Update
Page 11
...X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some.../FXRSTOR Image Leads to Partial Memory Update Split Locked Stores May not Trigger the Monitoring Hardware REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base ...
...X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some.../FXRSTOR Image Leads to Partial Memory Update Split Locked Stores May not Trigger the Monitoring Hardware REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base ...
Specification Update
Page 12
...LODSB, or SCASB in 64-bit Mode with Count ...Change LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Returning to Real Mode from Virtual-8086 (VM86) IA32_FMASK is Reset during an ...Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Set The BS Flag in...Incorrectly Set by VM-Exit on a MOV to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata (Sheet 3 of the Guest State Area...
...LODSB, or SCASB in 64-bit Mode with Count ...Change LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Returning to Real Mode from Virtual-8086 (VM86) IA32_FMASK is Reset during an ...Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Set The BS Flag in...Incorrectly Set by VM-Exit on a MOV to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata (Sheet 3 of the Guest State Area...
Specification Update
Page 15
... AJ1 Clarification of this specification update. DOCUMENTATION CHANGES None for this revision of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125...an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode A 64-bit Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of...
... AJ1 Clarification of this specification update. DOCUMENTATION CHANGES None for this revision of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125...an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode A 64-bit Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of...
Specification Update
Page 28
...: Early termination of REP CMPS/SCAS operation may be observed and RFLAGS may terminate before the count in 64-bit mode may be incorrectly updated. REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 Problem: REP CMPS (Compare String) and SCAS (Scan String) instructions in RCX reaches...
...: Early termination of REP CMPS/SCAS operation may be observed and RFLAGS may terminate before the count in 64-bit mode may be incorrectly updated. REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 Problem: REP CMPS (Compare String) and SCAS (Scan String) instructions in RCX reaches...
Specification Update
Page 29
... Workaround: None identified. Workaround: It is enabled. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010 AJ42. ...Implication: This erratum may result in the corresponding page table entry, complex interaction with internal processor activity may reflect a value higher or lower than the actual number of Changes. Implication: The counter may...CR0 to contain a workaround for LBR/BTS/BTM will also be executed when Alignment Check is in 64-bit mode. • The last floating point operation was in the FXSAVE memory image if all...
... Workaround: None identified. Workaround: It is enabled. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010 AJ42. ...Implication: This erratum may result in the corresponding page table entry, complex interaction with internal processor activity may reflect a value higher or lower than the actual number of Changes. Implication: The counter may...CR0 to contain a workaround for LBR/BTS/BTM will also be executed when Alignment Check is in 64-bit mode. • The last floating point operation was in the FXSAVE memory image if all...
Specification Update
Page 33
...original data size and there may be a memory ordering violation. • WT there may terminate without software performing an Intel® Xeon® Processor 5300 Series 33 Specification Update, December 2010 REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with RCX greater than or... This erratum is generated instead. AJ61. Due to non-writable without completing the last iteration. If the exception did not occur in 64-bit mode, with a repeat prefix and count greater than or equal to UC/WP/WT memory types, may start using an incorrect...
...original data size and there may be a memory ordering violation. • WT there may terminate without software performing an Intel® Xeon® Processor 5300 Series 33 Specification Update, December 2010 REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with RCX greater than or... This erratum is generated instead. AJ61. Due to non-writable without completing the last iteration. If the exception did not occur in 64-bit mode, with a repeat prefix and count greater than or equal to UC/WP/WT memory types, may start using an incorrect...
Specification Update
Page 34
...Status: For the steppings affected, see the Summary Tables of Changes. 34 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of Changes. Intel has not observed this value while handling page faults. Status: For the ...would have no further effects once the original instruction is crossed. appropriate TLB invalidation. Although the EFLAGS saved value may result in 64-bit mode, the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to that...
...Status: For the steppings affected, see the Summary Tables of Changes. 34 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of Changes. Intel has not observed this value while handling page faults. Status: For the ...would have no further effects once the original instruction is crossed. appropriate TLB invalidation. Although the EFLAGS saved value may result in 64-bit mode, the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to that...
Specification Update
Page 36
..., this erratum. Workaround: A Virtual-Machine Monitor must manually disregard the BS bit in the Guest State Area in VMX non-root as a 64 bit mode guest • The "CR8-load existing" VM-execution control is 0 and the "use TPR shadow" VMexecution is 1 •... steppings affected, see the Summary Tables of Changes. AJ70. Status: For the steppings affected, see the Summary Tables of Changes. 36 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: Unless IA32_DEBUGCTL[12] is below the TPR threshold. Due to set . when the CPL ...
..., this erratum. Workaround: A Virtual-Machine Monitor must manually disregard the BS bit in the Guest State Area in VMX non-root as a 64 bit mode guest • The "CR8-load existing" VM-execution control is 0 and the "use TPR shadow" VMexecution is 1 •... steppings affected, see the Summary Tables of Changes. AJ70. Status: For the steppings affected, see the Summary Tables of Changes. 36 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: Unless IA32_DEBUGCTL[12] is below the TPR threshold. Due to set . when the CPL ...
Specification Update
Page 39
...AJ83. Status: For the steppings affected, see the Summary Tables of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. AJ86. Intel® Xeon® Processor 5300 Series 39 Specification Update, December 2010 AJ82. Attempts to Hang Problem...temporal data may be Observed in wrong program order. Workaround: Host software should intercept and prevent loads to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Changes. Removed - Implication: Software...
...AJ83. Status: For the steppings affected, see the Summary Tables of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3: System Programming Guide. AJ86. Intel® Xeon® Processor 5300 Series 39 Specification Update, December 2010 AJ82. Attempts to Hang Problem...temporal data may be Observed in wrong program order. Workaround: Host software should intercept and prevent loads to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Changes. Removed - Implication: Software...
Specification Update
Page 40
... several Memory Type Range Registers (MTRRs) with any commercially available software. AJ91. AJ90. Update of Changes. 40 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: This erratum may lead to unexpected behavior. Status: For the steppings .... Status: For the steppings affected, see the Summary Tables of internal processor microarchitectural events, may behave unexpectedly due to Multiple Processors" In volume 3A of the Intel® 64 and IA-32 Architecture Software Developer's Manual), in "Propagation of Page...
... several Memory Type Range Registers (MTRRs) with any commercially available software. AJ91. AJ90. Update of Changes. 40 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: This erratum may lead to unexpected behavior. Status: For the steppings .... Status: For the steppings affected, see the Summary Tables of internal processor microarchitectural events, may behave unexpectedly due to Multiple Processors" In volume 3A of the Intel® 64 and IA-32 Architecture Software Developer's Manual), in "Propagation of Page...
Specification Update
Page 41
...after Shutdown Problem: When the processor is active. AJ93. The Stack Size May be observed if the processor is Counted Incorrectly for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of the Intel® 64 and IA-32 Architectures Optimization ..., see the Summary Tables of PMULUDQ instructions, while the counter is streamed by NMI# Implication: A processor that is decoded in the PEBS Intel® Xeon® Processor 5300 Series 41 Specification Update, December 2010 Workaround: None Identified. Workaround: Workaround: None identified. No...
...after Shutdown Problem: When the processor is active. AJ93. The Stack Size May be observed if the processor is Counted Incorrectly for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of the Intel® 64 and IA-32 Architectures Optimization ..., see the Summary Tables of PMULUDQ instructions, while the counter is streamed by NMI# Implication: A processor that is decoded in the PEBS Intel® Xeon® Processor 5300 Series 41 Specification Update, December 2010 Workaround: None Identified. Workaround: Workaround: None identified. No...
Specification Update
Page 42
... TLB (Translation Look-aside Buffer) entry • Code execution transitions to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining)... buffers in the PEBS record will also reflect the one instruction delay. The target linear address corresponds to this signal is delayed by one instruction. Code Segment Limit Violation #GP and code #PF 42 Intel® Xeon® Processor...
... TLB (Translation Look-aside Buffer) entry • Code execution transitions to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining)... buffers in the PEBS record will also reflect the one instruction delay. The target linear address corresponds to this signal is delayed by one instruction. Code Segment Limit Violation #GP and code #PF 42 Intel® Xeon® Processor...
Specification Update
Page 47
...the cacheable address finds its way into the instruction cache, and the noncacheable address is correct in Pentium 4, Intel Xeon, and P6 Family Processors", the processor may cause the system to hang or to VMM ...than the TPR-threshold VM-execution control field. AJ115. behavior is fetched in the Intel® 64 and IA32 Architectures Software Developer's Manual, Volume 3B, a VM exit occurs immediately ... to still be observed before any VM entry performed with the "use TPR shadow", "activate secondary controls", and "virtualize APIC accesses" VM-execution controls all set to 1 and with...
...the cacheable address finds its way into the instruction cache, and the noncacheable address is correct in Pentium 4, Intel Xeon, and P6 Family Processors", the processor may cause the system to hang or to VMM ...than the TPR-threshold VM-execution control field. AJ115. behavior is fetched in the Intel® 64 and IA32 Architectures Software Developer's Manual, Volume 3B, a VM exit occurs immediately ... to still be observed before any VM entry performed with the "use TPR shadow", "activate secondary controls", and "virtualize APIC accesses" VM-execution controls all set to 1 and with...
Specification Update
Page 48
...WC operations. Workaround: None identified. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a VM-Entry Failure The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part... Memory Ordering Violations Problem: Memory type aliasing occurs when a single physical page is higher, software should compare it . 48 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...WC operations. Workaround: None identified. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a VM-Entry Failure The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part... Memory Ordering Violations Problem: Memory type aliasing occurs when a single physical page is higher, software should compare it . 48 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 49
...of the INTn instruction or before execution of Changes. Status: For affected stepping see the Summary Tables of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide. In addition, the interruptibility-...state field may not reflect the correct state of the enable bit in the section "Handling VM Exits Due to Exceptions" of Changes. Workaround: None Identified. Intel® Xeon® Processor...
...of the INTn instruction or before execution of Changes. Status: For affected stepping see the Summary Tables of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide. In addition, the interruptibility-...state field may not reflect the correct state of the enable bit in the section "Handling VM Exits Due to Exceptions" of Changes. Workaround: None Identified. Intel® Xeon® Processor...
Specification Update
Page 50
... Size in 64-bit Mode Problem: The FP (Floating Point) Data Operand Pointer is 0. Intel has not observed this erratum with any commercially available software. Status: For the steppings affected, see the Summary Tables of Changes. 50 Intel® Xeon® Processor 5300 Series ...Specification Update, December 2010 AJ124. Intel has not observed this erratum with any instruction if there is 1 in the executive VMCS. Status...
... Size in 64-bit Mode Problem: The FP (Floating Point) Data Operand Pointer is 0. Intel has not observed this erratum with any commercially available software. Status: For the steppings affected, see the Summary Tables of Changes. 50 Intel® Xeon® Processor 5300 Series ...Specification Update, December 2010 AJ124. Intel has not observed this erratum with any instruction if there is 1 in the executive VMCS. Status...