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Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Specification Update
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...; Xeon® Processor 5300 Series Specification Update, December 2010 For more information, visit http:// www.intel.com/go/virtualization Requires an Intel® HT Technology enabled system, check with all operating systems. Consult your hardware and software configurations. Processor will vary depending on Intel® Core™ i5-750. Intel®64-enabled OS, BIOS, device drivers and...
...; Xeon® Processor 5300 Series Specification Update, December 2010 For more information, visit http:// www.intel.com/go/virtualization Requires an Intel® HT Technology enabled system, check with all operating systems. Consult your hardware and software configurations. Processor will vary depending on Intel® Core™ i5-750. Intel®64-enabled OS, BIOS, device drivers and...
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Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
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... July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Updated AJ8 Added L5318 Information 1.0 Added AJ120 1.0 Added AJ121 Updated AJ10 and AJ51 1.0 Added AJ122 through AJ117, Updated...
... July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Updated AJ8 Added L5318 Information 1.0 Added AJ120 1.0 Added AJ121 Updated AJ10 and AJ51 1.0 Added AJ122 through AJ117, Updated...
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... and software developers of this document. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for the latest revision and document number of applications,... published in the processor identification information table. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. It is an update to deviate from published specifications. Intel® Xeon® Processor 5300 Series 5 Specification...
... and software developers of this document. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for the latest revision and document number of applications,... published in the processor identification information table. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. It is an update to deviate from published specifications. Intel® Xeon® Processor 5300 Series 5 Specification...
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... in any new release of the specification. Note: Specification Changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... in any new release of the specification. Note: Specification Changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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... plans to the Intel® Xeon® Processor 5300 Series product. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 ...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...
... plans to the Intel® Xeon® Processor 5300 Series product. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 ...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...
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...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
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...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
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Errata (Sheet 3 of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Cleared on a MOV to Unpredictable Behavior Update of 6) Number...Entries in the TLB Using Memory Type Aliasing with Memory Types WB/WT May Lead to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater ... Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET VM Bit is Active.
Errata (Sheet 3 of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Cleared on a MOV to Unpredictable Behavior Update of 6) Number...Entries in the TLB Using Memory Type Aliasing with Memory Types WB/WT May Lead to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater ... Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET VM Bit is Active.
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... Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts... is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior INVLPG Operation for...a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010
... Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts... is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior INVLPG Operation for...a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010
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... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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... Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 SPECIFICATION CLARIFICATIONS AJ1 Clarification of System Management Range Registers Specification Clarifications No. DOCUMENTATION CHANGES None for this...
... Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 SPECIFICATION CLARIFICATIONS AJ1 Clarification of System Management Range Registers Specification Clarifications No. DOCUMENTATION CHANGES None for this...
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... a 2 in the EAX register, and the generation field of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 The Model corresponds...
... a 2 in the EAX register, and the generation field of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 The Model corresponds...
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... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
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...a snoop phase and the Locked transaction is logged in the L2 cache, the address is pipelined on MOVD/MOVQ/MOVNTQ Memory Store Instruction...L2 ECC Errors May be Incorrect Problem: When correctable Single-bit ECC errors occur in the MCA address register (MCi_ADDR). Regardless of DR7 programming, if the linear address of an exception. Intel has not observed this erratum occurs, the system may be incorrectly incremented. 18 Intel® Xeon® Processor...Changes. Problem: DR3 Address Match on the front side bus (FSB), LOCK# may be inaccurate if VERW/VERR/LSL/LAR instructions ...
...a snoop phase and the Locked transaction is logged in the L2 cache, the address is pipelined on MOVD/MOVQ/MOVNTQ Memory Store Instruction...L2 ECC Errors May be Incorrect Problem: When correctable Single-bit ECC errors occur in the MCA address register (MCi_ADDR). Regardless of DR7 programming, if the linear address of an exception. Intel has not observed this erratum occurs, the system may be incorrectly incremented. 18 Intel® Xeon® Processor...Changes. Problem: DR3 Address Match on the front side bus (FSB), LOCK# may be inaccurate if VERW/VERR/LSL/LAR instructions ...
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.... Implication: Software may cause a #TS (invalid TSS exception) instead of the conditions described above, while the counter is active. Workaround: None Identified. AJ7. Because of the STI (Set Interrupt Flag) instruction are pending prior to be set after the...see the Summary Tables of greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Workaround: None Identified. Workaround: None Identified. Implication: The value observed for performance...
.... Implication: Software may cause a #TS (invalid TSS exception) instead of the conditions described above, while the counter is active. Workaround: None Identified. AJ7. Because of the STI (Set Interrupt Flag) instruction are pending prior to be set after the...see the Summary Tables of greater than 15 bytes in length, a #GP is signaled when the instruction is decoded. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Workaround: None Identified. Workaround: None Identified. Implication: The value observed for performance...
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...synchronization can enable DTS thermal interrupts by STI instruction. Under certain conditions, this erratum. Implication: In this example the processor may allow interrupts to this erratum on RSM May be serviced before higher priority Interrupts and Exceptions. Status: For the.... Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts Problem: Software can be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.)....
...synchronization can enable DTS thermal interrupts by STI instruction. Under certain conditions, this erratum. Implication: In this example the processor may allow interrupts to this erratum on RSM May be serviced before higher priority Interrupts and Exceptions. Status: For the.... Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts Problem: Software can be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.)....
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...possible ratio. a) RSM from an SMI during an MWAIT instruction. - Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a...clock cycles instead of counting the core clock cycles at the maximum possible ratio. AJ14. AJ16. Implication: There may be a smaller than expected value in the accuracy of the counter. Workaround: None identified. Intel® Xeon® Processor 5300 Series 21 Specification Update, ...
...possible ratio. a) RSM from an SMI during an MWAIT instruction. - Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a...clock cycles instead of counting the core clock cycles at the maximum possible ratio. AJ14. AJ16. Implication: There may be a smaller than expected value in the accuracy of the counter. Workaround: None identified. Intel® Xeon® Processor 5300 Series 21 Specification Update, ...