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Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Specification Update
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... have no responsibility whatsoever for more information See the Processor Spec Finder at http://ark.intel.com or contact your Intel representative for conflicts or incompatibilities arising from published specifications. and other benefits will vary depending on Intel® Core™ i5-750. The Intel® Xeon® Processor 5300 Series may cause the product to deviate from...
... have no responsibility whatsoever for more information See the Processor Spec Finder at http://ark.intel.com or contact your Intel representative for conflicts or incompatibilities arising from published specifications. and other benefits will vary depending on Intel® Core™ i5-750. The Intel® Xeon® Processor 5300 Series may cause the product to deviate from...
Specification Update
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Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
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... 2007 July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Revision History Revision -001 -002 -003 -004 -005 Version 1.0 1.0 1.0 1.0 1.0 Description Initial Release Deleted AJ83 and AJ87...
... 2007 July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Revision History Revision -001 -002 -003 -004 -005 Version 1.0 1.0 1.0 1.0 1.0 Description Initial Release Deleted AJ83 and AJ87...
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... by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 as described in the Affected Documents table below. These may also contain information that stepping are no longer published in other documents. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number...
... by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 as described in the Affected Documents table below. These may also contain information that stepping are no longer published in other documents. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number...
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.... Under these circumstances, errata removed from the specification update are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Note: Specification Changes are modifications to a complex design situation. Documentation Changes include typos, errors, or omissions from the...
.... Under these circumstances, errata removed from the specification update are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Note: Specification Changes are modifications to a complex design situation. Documentation Changes include typos, errors, or omissions from the...
Specification Update
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...; processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with a capital letter to fix this erratum. This erratum may fix some of the errata in a future stepping of the product. This erratum is prefixed with 1MB L2 cache...
...; processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with a capital letter to fix this erratum. This erratum may fix some of the errata in a future stepping of the product. This erratum is prefixed with 1MB L2 cache...
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...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
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...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
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... Incorrectly INIT Does Not Clear Global Entries in the TLB Using Memory Type Aliasing with Memory Types WB/WT May Lead to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata (Sheet 3 of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected...
... Incorrectly INIT Does Not Clear Global Entries in the TLB Using Memory Type Aliasing with Memory Types WB/WT May Lead to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata (Sheet 3 of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected...
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... Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for PMULUDQ Instruction Storage of PEBS Record Delayed Following Execution of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Not Applicable...
... Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for PMULUDQ Instruction Storage of PEBS Record Delayed Following Execution of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Not Applicable...
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... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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DOCUMENTATION CHANGES None for this specification update. SPECIFICATION CLARIFICATIONS AJ1 Clarification of this revision of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No Fix No Fix No Fix AJ126 X X No Fix ...
DOCUMENTATION CHANGES None for this specification update. SPECIFICATION CLARIFICATIONS AJ1 Clarification of this revision of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No Fix No Fix No Fix AJ126 X X No Fix ...
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... generation field of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 LAOTTPONO S/N The Quad-Core Intel® Xeon® Processor 5300 Series stepping...
... generation field of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 LAOTTPONO S/N The Quad-Core Intel® Xeon® Processor 5300 Series stepping...
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... E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
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...updated, if the resultant value of the Zero Flag (ZF) is logged in the L2 cache, the address is zero after executing the following instructions 1) VERR (ZF=0 indicates unsuccessful...the address in MCi_ADDR, for Event CFH normally increments on the front side bus (FSB), LOCK# may be incorrect. Problem: DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory...programming, if the linear address of Changes. Intel has not observed this erratum occurs, the system may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata AJ1...
...updated, if the resultant value of the Zero Flag (ZF) is logged in the L2 cache, the address is zero after executing the following instructions 1) VERR (ZF=0 indicates unsuccessful...the address in MCi_ADDR, for Event CFH normally increments on the front side bus (FSB), LOCK# may be incorrect. Problem: DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory...programming, if the linear address of Changes. Intel has not observed this erratum occurs, the system may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata AJ1...
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...Instructions Greater than 15 bytes in the RFLAGS Register Problem: In normal operation, SYSRET will be Preempted Problem: When the processor encounters an instruction that are pending prior to a busy TSS (Task-State Segment) may observe a lower-priority fault ...active. Page Fault (#PF)). Workaround: None Identified. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Problem: Interrupts that is decoded. Status: For the steppings affected, see the Summary Tables of the SYSRET instruction. AJ8. Intel® Xeon® Processor...
...Instructions Greater than 15 bytes in the RFLAGS Register Problem: In normal operation, SYSRET will be Preempted Problem: When the processor encounters an instruction that are pending prior to a busy TSS (Task-State Segment) may observe a lower-priority fault ...active. Page Fault (#PF)). Workaround: None Identified. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Problem: Interrupts that is decoded. Status: For the steppings affected, see the Summary Tables of the SYSRET instruction. AJ8. Intel® Xeon® Processor...
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...a non-canonical address, the address pushed onto the stack for Performance-Monitoring Counter PMH_PAGE_WALK May be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: In the ACPI/OS implement a workaround by programming the thermal threshold ... before higher priority Interrupts and Exceptions. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). Intel has not observed this erratum. Code Segment Limit/Canonical Faults on any subsequent instructions are not lost. For example if...
...a non-canonical address, the address pushed onto the stack for Performance-Monitoring Counter PMH_PAGE_WALK May be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: In the ACPI/OS implement a workaround by programming the thermal threshold ... before higher priority Interrupts and Exceptions. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). Intel has not observed this erratum. Code Segment Limit/Canonical Faults on any subsequent instructions are not lost. For example if...
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...iteration of Changes. Performance Monitoring Events for this value is smaller than expected is computed by dividing the maximum possible core frequency by exactly one multiple of the counter. Workaround: None identified. Implication: The CPU_CLK_UNHALTED performance monitor with an ... • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are also not counted: - Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 Implication: There may be a smaller than expected. AJ16. The maximum possible ...
...iteration of Changes. Performance Monitoring Events for this value is smaller than expected is computed by dividing the maximum possible core frequency by exactly one multiple of the counter. Workaround: None identified. Implication: The CPU_CLK_UNHALTED performance monitor with an ... • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are also not counted: - Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 Implication: There may be a smaller than expected. AJ16. The maximum possible ...