Specification Update
Page 1
...; Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update...
...; Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update...
Specification Update
Page 2
... operation) without notice. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update and other Intel Trusted Execution Technology compatible measured virtual machine monitor. Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are not intended for Intel 64. Enabling Execute Disable Bit functionality requires...
... operation) without notice. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update and other Intel Trusted Execution Technology compatible measured virtual machine monitor. Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are not intended for Intel 64. Enabling Execute Disable Bit functionality requires...
Specification Update
Page 4
...Jan 2007 Out Of Cycle Feb 2007 Mar 2007 Apr 2007 Apr 2007 Out Of Cycle 4 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI100 • Added Erratum AI101-AI104 • Updated ...Erratum AI33 in Summary table of changes • Added processor number E6320, E6420 and E4400 information Date July 2006 Out of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated Erratum AI19, AI29 and...
...Jan 2007 Out Of Cycle Feb 2007 Mar 2007 Apr 2007 Apr 2007 Out Of Cycle 4 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI100 • Added Erratum AI101-AI104 • Updated ...Erratum AI33 in Summary table of changes • Added processor number E6320, E6420 and E4400 information Date July 2006 Out of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated Erratum AI19, AI29 and...
Specification Update
Page 5
...8226; Updated Erratum AI51 • Deleted Erratum AI123 (because it is repeat of AI108) and replaced with a new Erratum • Added processor number E4700 information • Added Erratum AI127, AI128 -027 • Added Erratum AI129 Date Apr 2007 Out Of Cycle May 2007 July ...Oct 2007 Nov 2007 Dec 2007 Jan 16th 2008 Feb 13th 2008 Mar 3rd 2008 May 2008 December 8th, 2010 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update AI42, AI44, AI50, AI55 - AI123 • Updated Plan Status for...
...8226; Updated Erratum AI51 • Deleted Erratum AI123 (because it is repeat of AI108) and replaced with a new Erratum • Added processor number E4700 information • Added Erratum AI127, AI128 -027 • Added Erratum AI129 Date Apr 2007 Out Of Cycle May 2007 July ...Oct 2007 Nov 2007 Dec 2007 Jan 16th 2008 Feb 13th 2008 Mar 3rd 2008 May 2008 December 8th, 2010 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update AI42, AI44, AI50, AI55 - AI123 • Updated Plan Status for...
Specification Update
Page 6
...; 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update This document may also contain information that has not been previously published. Preface Preface This...
...; 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update This document may also contain information that has not been previously published. Preface Preface This...
Specification Update
Page 7
...core speed, L2 cache size, package type, etc.) as described in the next release of the specifications. Errata may cause the processor's behavior to deviate from the current published specifications. These changes will be incorporated in the processor identification information table. The NDA specification update has a processor... or user documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7 Specification Update Preface Nomenclature S-Spec...
...core speed, L2 cache size, package type, etc.) as described in the next release of the specifications. Errata may cause the processor's behavior to deviate from the current published specifications. These changes will be incorporated in the processor identification information table. The NDA specification update has a processor... or user documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7 Specification Update Preface Nomenclature S-Spec...
Specification Update
Page 8
Intel intends to fix some of the errata in a future stepping of the product. Status Doc: PlanFix: Fixed: NoFix: Document change does not apply to listed ... this stepping. (No mark) or (Blank Box): This erratum is either new or modified from the previous version of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Row Shaded: This item is fixed in listed stepping or specification change or update that applies...
Intel intends to fix some of the errata in a future stepping of the product. Status Doc: PlanFix: Fixed: NoFix: Document change does not apply to listed ... this stepping. (No mark) or (Blank Box): This erratum is either new or modified from the previous version of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Row Shaded: This item is fixed in listed stepping or specification change or update that applies...
Specification Update
Page 9
... = Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel®...
... = Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel®...
Specification Update
Page 10
...#GP Fault 10 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update NO B1 B2 L2 M0 G0 Plan ...L2 ECC Errors May be Incorrect AI4 X X X X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR DR3 Address Match on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel...
...#GP Fault 10 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update NO B1 B2 L2 M0 G0 Plan ...L2 ECC Errors May be Incorrect AI4 X X X X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR DR3 Address Match on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel...
Specification Update
Page 11
... Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI10 X...AI17 X X X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line AI18 X X X X X No Fix ...-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24...Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
... Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI10 X...AI17 X X X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line AI18 X X X X X No Fix ...-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24...Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
Specification Update
Page 12
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper ...
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper ...
Specification Update
Page 13
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI52 X X X X X No Fix Last Branch Records (LBR) Updates May ...AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active AI58 X X X X X... Event FP_ASSIST May Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI52 X X X X X No Fix Last Branch Records (LBR) Updates May ...AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active AI58 X X X X X... Event FP_ASSIST May Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
Specification Update
Page 14
...X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No... Non-root Operation Could Result in Unexpected Behavior AI89 X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AI90 X X X X X No Fix Page Access Bit May be Set ... and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
...X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No... Non-root Operation Could Result in Unexpected Behavior AI89 X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AI90 X X X X X No Fix Page Access Bit May be Set ... and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
Specification Update
Page 15
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AI97 X X X X X No Fix ... Result in a Processor Hang AI115 X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 ...
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AI97 X X X X X No Fix ... Result in a Processor Hang AI115 X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 ...
Specification Update
Page 16
...Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Number SPECIFICATION CLARIFICATIONS AI1 Clarification of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI117 X X X X X...A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES - There are Not Cleared When the Processor is Reset AI122 X Fixed VTPR Access May Lead to System Hang AI123 X Fixed IA32_MC1_STATUS MSR Bit[60] Does Not...
...Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Number SPECIFICATION CLARIFICATIONS AI1 Clarification of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI117 X X X X X...A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES - There are Not Cleared When the Processor is Reset AI122 X Fixed VTPR Access May Lead to System Hang AI123 X Fixed IA32_MC1_STATUS MSR Bit[60] Does Not...
Specification Update
Page 17
Intel® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N Figure 2. Identification Information Identification Information Figure 1. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 Specification Update
Intel® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N Figure 2. Identification Information Identification Information Figure 1. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 Specification Update
Specification Update
Page 20
... Technology (Intel® TXT) 6. Cache and TLB descriptor parameters are applicable to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 2 in the EAX register, and the generation field of 8W 20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000...
... Technology (Intel® TXT) 6. Cache and TLB descriptor parameters are applicable to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 2 in the EAX register, and the generation field of 8W 20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000...
Specification Update
Page 21
..., 12, 13, 15 775-land LGA 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update Intel® Core™2 Duo Desktop Processor 2M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9SA B2 2M 06F6h E6300 SL9S9 B2 2M 06F6h E6400 SL9TB...
..., 12, 13, 15 775-land LGA 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update Intel® Core™2 Duo Desktop Processor 2M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9SA B2 2M 06F6h E6300 SL9S9 B2 2M 06F6h E6400 SL9TB...
Specification Update
Page 22
... Information Table 2. Intel® Core™2 Extreme Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel® Core™2 Duo Desktop Processor 4M SKU Identification...
... Information Table 2. Intel® Core™2 Extreme Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel® Core™2 Duo Desktop Processor 4M SKU Identification...
Specification Update
Page 23
...Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during shutdown. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update The ISR associated ... register (MCi_ADDR). Implication: Software should not be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is set in the in-service register and mask all interrupts at the same or lower priority. ...
...Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during shutdown. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update The ISR associated ... register (MCi_ADDR). Implication: Software should not be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is set in the in-service register and mask all interrupts at the same or lower priority. ...