Intel E5345 - Xeon 2.33 GHz 8M L2 Cache 1333MHz FSB LGA771 Active Quad-Core Processor Support and Manuals
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Specification Update - Page 5
... Programming Guide Intel® 64 and IA-32 Intel Architecture Optimization Reference Manual
http://www.intel.com/ products/processor/ manuals/index.htm
Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes
http://www.intel.com/ design/processor/specupdt/
252046.htm
Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture...
Specification Update - Page 13
... Paging Structures May Cause the Processor to Unexpected Behavior
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown
Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions
The Stack Size May be Incorrect as a Result of MOV SS or STI
Intel® Xeon® Processor 5300 Series
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Specification Update, December 2010
Specification Update - Page 16
... registers after the CPUID instruction is executed with a 1 in the EAX register. LAOTTPONO S/N
The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings:
Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2)
Processor S-Spec Number
Core Stepping
CPUID
Core Freq (GHz)
Data Bus Freq (MHz...
Specification Update - Page 19
... a #GP fault (general protection exception).
Intel® Xeon® Processor 5300 Series
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Specification Update, December 2010 AJ7. However, if the preempting lower priority faults are serviced immediately after execution of the SYSCALL instruction). Instructions of greater than 15 bytes in length can not be used if the RF flag needs to be set after returning from a system call...
Specification Update - Page 20
... to not be serviced until the interrupt enabled flag is generated after an uncacheable ...Problem:
Software can be incorrect.
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Intel® Xeon® Processor 5300 Series
Specification Update, December 2010 Due to the Task Priority Register (TPR) that caused the fault. If the RSM attempts to return to code execution, a #GP (General Protection Exception) fault is finally set, i.e. Intel...
Specification Update - Page 29
...Changes.
Problem:
Values for BIOS to the same non-dirty page or explicitly sets the dirty bit in compatibility mode
• Bit 31 of the 3 above mentioned debug support facilities are true:
• The processor is in 64-bit mode... the expected value of the following conditions are used. Intel® Xeon® Processor 5300 Series
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Specification Update, December 2010
AJ41.
Specification Update - Page 31
...Due to generate a synchronous SMI for the recorded I /O port. The SMM handler must not restart an I/O instruction if the platform has not been configured to this instruction is Followed by an Instruction That Signals a Floating Point Exception
Problem:
A MOV SS/POP SS instruction should be executed atomically. Intel® Xeon® Processor 5300 Series
31
Specification Update, December...
Specification Update - Page 38
... is returning from CPL3 code to the same address the first load may violate proper store ordering. In systems supporting Intel® Virtualization Technology, when the processor is possible for this erratum with IRET.
This behavior depends on the stack has the AC flag set to contain a workaround for BIOS to 1, a MOV instruction from CPL0/1/2 are disabled...
Data Sheet - Page 9
... Machine
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
9 The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® 64 architecture as executable or non executable.
Enhanced thermal and power management capabilities are 64-bit server/workstation processors utilizing four Intel Core™ microarchitecture cores.
Intel Virtualization...
Data Sheet - Page 10
... The processors support a Dual Independent Bus (DIB) architecture with 771 lands for implementation details. The FSB is also used to Section 1.3).
10
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet The DIB architecture provides improved performance by VRM/EVRD 11.0 and its associated load line (see Section 2.13.1). Section 2.1 contains the electrical specifications of...
Data Sheet - Page 26
... will not be satisfied. 2. Electrical Specifications
2.11
Note:
Mixing Processors
Intel supports and validates dual processor configurations only in which lie outside these...processor.
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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Details regarding the CPUID instruction are provided in the AP-485 Intel® Processor Identification and the CPUID Instruction...
Data Sheet - Page 32
... that will be interpreted as the minimum voltage level at the pin.
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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet This is the instantaneous VTT. 7. The VTT referred to processor I /V characteristics. Electrical Specifications
Figure 2-5. Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and Transient Tolerance Load Lines
Vcc [V]
0 V ID - 0.000...
Data Sheet - Page 34
... and GTLREF_ADD_END are the reference voltage for implementation details.
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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Refer to the appropriate platform design guidelines for RTT values. These measurements of processor die level overshoot should be generated on the processors supported and the chipset used in duration may be ignored.
Overshoot events...
Data Sheet - Page 87
... to cause the Quad-Core Intel® Xeon® Processor 5300 Series to activate the TCC. Refer to the Intel® 64 and IA-32 Architecture Software Developer's Manual for details on /12.5% off in conjunction with the Thermal Monitor; Refer to the appropriate platform design guidelines for specific register and programming details. Thermal Specifications
6.2.5 6.2.6
be programmed from...
Data Sheet - Page 92
... transitions in the Extended HALT state, the processor will process bus snoops.
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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume III: System Programming Guide for more information.
however, the other processor cores continue normal operation. Extended HALT State...
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