Specification Update
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... specifications contained in other documents. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 These may also contain information that stepping are no longer published in the Affected Documents table below. It is a five-digit code used with any given stepping must assume that all notes associated with each S-Spec number. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number...
... specifications contained in other documents. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 These may also contain information that stepping are no longer published in the Affected Documents table below. It is a five-digit code used with any given stepping must assume that all notes associated with each S-Spec number. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number...
Specification Update
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... are used in listed stepping or specification change or update will be fixed in a future stepping of item in the stepping indicated. Row A = C = D = E = F = I = J = K = Each Specification Update item is fixed in Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon...
... are used in listed stepping or specification change or update will be fixed in a future stepping of item in the stepping indicated. Row A = C = D = E = F = I = J = K = Each Specification Update item is fixed in Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon...
Specification Update
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...-KB L2 cache Intel® Pentium® M processor Mobile Intel® Pentium® 4 processor with 533 MHz system bus Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965 Intel® Pentium® 4 processor 6x1 sequence Intel® Celeron® processor in 478 pin package Intel® Celeron® D processor on 65nm_process Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Intel® Xeon® processor LV Intel® Xeon® processor...
...-KB L2 cache Intel® Pentium® M processor Mobile Intel® Pentium® 4 processor with 533 MHz system bus Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965 Intel® Pentium® 4 processor 6x1 sequence Intel® Celeron® processor in 478 pin package Intel® Celeron® D processor on 65nm_process Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Intel® Xeon® processor LV Intel® Xeon® processor...
Specification Update
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... of 6) Number Steppings B-3 G-0 ...Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some Bus Performance...Supported (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction...
... of 6) Number Steppings B-3 G-0 ...Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some Bus Performance...Supported (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction...
Specification Update
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... WT Memory Data May be Seen in Wrong Program Order Removed - Not Applicable Non-Temporal Data Store May be Observed in Wrong Order by Two Subsequent Loads IRET under Certain Conditions Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December...
... WT Memory Data May be Seen in Wrong Program Order Removed - Not Applicable Non-Temporal Data Store May be Observed in Wrong Order by Two Subsequent Loads IRET under Certain Conditions Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December...
Specification Update
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... 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 The Model corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction...
... 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 The Model corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction...
Specification Update
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... Power) 6. These parts have Execute Disable bit functionality. 9. f Intel® Xeon® Processor 5300 Series Identification Information (Sheet 2 of 2) Processor S-Spec Number SLAC5 SL9YK SLAC7 SL9MV SLAC8 SL9XR SLACB SLA4Q SLAC9 SL9MT SLACA SLAEG SLAEJ SLAEK SLAEL SLAEM SLAEP SLAEQ E5345 E5335 E5335 E5320 E5320 E5310 E5310 L5320 L5320 L5310 L5310 X5355 E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7...
... Power) 6. These parts have Execute Disable bit functionality. 9. f Intel® Xeon® Processor 5300 Series Identification Information (Sheet 2 of 2) Processor S-Spec Number SLAC5 SL9YK SLAC7 SL9MV SLAC8 SL9XR SLACB SLA4Q SLAC9 SL9MT SLACA SLAEG SLAEJ SLAEK SLAEL SLAEM SLAEP SLAEQ E5345 E5335 E5335 E5320 E5320 E5310 E5310 L5320 L5320 L5310 L5310 X5355 E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7...
Specification Update
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.... Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Due to the execution of Changes. Status: For the steppings affected, see the Summary Tables of the conditions described above, while the counter is dependent on the number of occurrences of Changes. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Problem...
.... Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Due to the execution of Changes. Status: For the steppings affected, see the Summary Tables of the conditions described above, while the counter is dependent on the number of occurrences of Changes. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Problem...
Specification Update
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... observe a #GP fault being serviced before the actual priority has been lowered. AJ13. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to be impacted by this counter may be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: This non...
... observe a #GP fault being serviced before the actual priority has been lowered. AJ13. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to be impacted by this counter may be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: This non...
Specification Update
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... (Branch Trace Store), hence rendering their data invalid. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010 PREFETCHh Instructions May Not be Accurate Problem: Performance monitoring events that count the number of Changes. AJ42. Implication: This erratum may not be Incorrect after FXSAVE Problem: The upper 32 bits of Changes. Status: For the steppings affected, see the Summary Tables of...
... (Branch Trace Store), hence rendering their data invalid. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010 PREFETCHh Instructions May Not be Accurate Problem: Performance monitoring events that count the number of Changes. AJ42. Implication: This erratum may not be Incorrect after FXSAVE Problem: The upper 32 bits of Changes. Status: For the steppings affected, see the Summary Tables of...
Specification Update
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... of the Branch Instruction. AJ51. This results in incorrect signaling of Changes. Intel® Xeon® Processor 5300 Series 31 Specification Update, December 2010 Last Branch Records (LBR) Updates May be executed atomically. Implication: The LBR_FROM will not generate a floating point exception. AJ50. Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS...
... of the Branch Instruction. AJ51. This results in incorrect signaling of Changes. Intel® Xeon® Processor 5300 Series 31 Specification Update, December 2010 Last Branch Records (LBR) Updates May be executed atomically. Implication: The LBR_FROM will not generate a floating point exception. AJ50. Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS...
Specification Update
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...; Xeon® Processor 5300 Series Specification Update, December 2010 AJ78. This behavior depends on the stack has the AC flag set to 1, a MOV instruction from CR8 with 16 Bit Operand Size Will Leave Bits 63:16 of the Destination Register Unmodified Problem: Moves to WT aliasing. Status: For the steppings affected, see the Summary Tables of the IRET. In systems supporting Intel...
...; Xeon® Processor 5300 Series Specification Update, December 2010 AJ78. This behavior depends on the stack has the AC flag set to 1, a MOV instruction from CR8 with 16 Bit Operand Size Will Leave Bits 63:16 of the Destination Register Unmodified Problem: Moves to WT aliasing. Status: For the steppings affected, see the Summary Tables of the IRET. In systems supporting Intel...
Data Sheet
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..., BIOS, device drivers and applications may cause the product to specifications and product descriptions at http://www3.intel.com/cd/ids/developer/asmo-na/eng/149308.htm. Copyright © 2006, Intel Corporation 2 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as the property of Intel Corporation or its...
..., BIOS, device drivers and applications may cause the product to specifications and product descriptions at http://www3.intel.com/cd/ids/developer/asmo-na/eng/149308.htm. Copyright © 2006, Intel Corporation 2 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as the property of Intel Corporation or its...
Data Sheet
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... hardware enhancements that can be marked as an enhancement to the L2 cache before an L1 cache requests occurs, resulting in high temperature situations. TM1 and TM2 provide efficient and effective cooling in reduced bus cycle penalties and improved performance. The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® 64 architecture as executable or non executable. This enhancement...
... hardware enhancements that can be marked as an enhancement to the L2 cache before an L1 cache requests occurs, resulting in high temperature situations. TM1 and TM2 provide efficient and effective cooling in reduced bus cycle penalties and improved performance. The Quad-Core Intel® Xeon® Processor 5300 Series supports Intel® 64 architecture as executable or non executable. This enhancement...
Data Sheet
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... details. The DIB architecture provides improved performance by VRM/EVRD 11.0 and its associated load line (see Section 2.13.1). It utilizes a surface mount LGA771 socket that supports Direct Socket Loading (DSL). Section 2.1 contains the electrical specifications of address and data to the appropriate platform design guidelines for each bus, up to Section 1.3). 10 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
... details. The DIB architecture provides improved performance by VRM/EVRD 11.0 and its associated load line (see Section 2.13.1). It utilizes a surface mount LGA771 socket that supports Direct Socket Loading (DSL). Section 2.1 contains the electrical specifications of address and data to the appropriate platform design guidelines for each bus, up to Section 1.3). 10 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Data Sheet
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... Quad-Core Intel® Xeon® Processor X5300 Series. L2 cache and system bus interface are unique to call out specifications that are explained here for the "Quad-Core Intel® Xeon® Processor 5300 Series". The electrical interface that are shared between the processor and chipset over the FSB. Intel 64-bit microprocessor intended for details regarding this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for dual processor...
... Quad-Core Intel® Xeon® Processor X5300 Series. L2 cache and system bus interface are unique to call out specifications that are explained here for the "Quad-Core Intel® Xeon® Processor 5300 Series". The electrical interface that are shared between the processor and chipset over the FSB. Intel 64-bit microprocessor intended for details regarding this surface mount, 771 Land socket. See the LGA771 Socket Design Guidelines for dual processor...
Data Sheet
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... 266.666 MHz Bus Clock 1.60 GHz 1.86 GHz 2.13 GHz 2.40 GHz Notes 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 Notes: 1. Individual processors operate only at the same core and FSB frequency. Please refer to select the FSB frequency. Listed frequencies are used to Table 2-15 for further details. Core Frequency to FSB Multiplier Configuration Core Frequency to the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. 4. BSEL[2:0] are CMOS outputs which...
... 266.666 MHz Bus Clock 1.60 GHz 1.86 GHz 2.13 GHz 2.40 GHz Notes 1, 2, 3, 4 1, 2, 3 1, 2, 3 1, 2, 3 Notes: 1. Individual processors operate only at the same core and FSB frequency. Please refer to select the FSB frequency. Listed frequencies are used to Table 2-15 for further details. Core Frequency to FSB Multiplier Configuration Core Frequency to the Quad-Core Intel® Xeon® Processor 5300 Series Specification Update. 4. BSEL[2:0] are CMOS outputs which...
Data Sheet
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.... VIH is defined as a logical low value. 3. The VTT referred to the appropriate platform design guide for VCCStatic and Transient Tolerance 4. Please refer to in this table apply to Table 2-13 for details...specifications. 2. Table 2-14. Unless otherwise noted, all processor frequencies. 2. However, input signal drivers must also be interpreted as the maximum voltage level at a receiving agent that will be taken from VTT with the signal quality specifications. 5. This is the measurement at the pin. 32 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
.... VIH is defined as a logical low value. 3. The VTT referred to the appropriate platform design guide for VCCStatic and Transient Tolerance 4. Please refer to in this table apply to Table 2-13 for details...specifications. 2. Table 2-14. Unless otherwise noted, all processor frequencies. 2. However, input signal drivers must also be interpreted as the maximum voltage level at a receiving agent that will be taken from VTT with the signal quality specifications. 5. This is the measurement at the pin. 32 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Data Sheet
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... is determined by value of VCC overshoot above VID Max 50 25 Units mV µs Figure 2-6 2-6 Notes Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 33 This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the measurement at 0.1*VTT. 5. These specifications apply to all specifications in this table apply to the processor die voltage as measured across the VCC_DIE_SENSE and...
... is determined by value of VCC overshoot above VID Max 50 25 Units mV µs Figure 2-6 2-6 Notes Quad-Core Intel® Xeon® Processor 5300 Series Datasheet 33 This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the measurement at 0.1*VTT. 5. These specifications apply to all specifications in this table apply to the processor die voltage as measured across the VCC_DIE_SENSE and...
Data Sheet
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.... Table 2-18 lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END specifications. Please refer to Table 2-18 for implementation details. 34 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Refer to the appropriate platform design guidelines for details on which signals do not include on the processors supported and the chipset used in the design. In most cases, termination resistors are...
.... Table 2-18 lists the GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END specifications. Please refer to Table 2-18 for implementation details. 34 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Refer to the appropriate platform design guidelines for details on which signals do not include on the processors supported and the chipset used in the design. In most cases, termination resistors are...
