Specification Update
Page 1
Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Specification Update
Page 2
... applications. Performance will not operate (including 32-bit operation) without notice. The Intel® Xeon® Processor 5300 Series may make changes to obtain the latest specifications and before placing your PC manufacturer. Not available on Intel® Core™ i5-750. Intel may contain design defects or errors known as the property of any time...
... applications. Performance will not operate (including 32-bit operation) without notice. The Intel® Xeon® Processor 5300 Series may make changes to obtain the latest specifications and before placing your PC manufacturer. Not available on Intel® Core™ i5-750. Intel may contain design defects or errors known as the property of any time...
Specification Update
Page 3
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Specification Update
Page 4
... July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Deleted AJ82 and AJ84. Updated AJ8 Added L5318 Information 1.0 Added AJ120 1.0 Added AJ121 Updated AJ10 and AJ51 1.0 Added...
... July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Deleted AJ82 and AJ84. Updated AJ8 Added L5318 Information 1.0 Added AJ120 1.0 Added AJ121 Updated AJ10 and AJ51 1.0 Added...
Specification Update
Page 5
... deviate from published specifications. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for hardware system manufacturers and software developers of applications, operating systems, or tools. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. S-Spec Number is...
... deviate from published specifications. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for hardware system manufacturers and software developers of applications, operating systems, or tools. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. S-Spec Number is...
Specification Update
Page 6
... clarifications will be incorporated in greater detail or further highlight a specification's impact to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Note: Specification Changes are made to a complex design situation.
... clarifications will be incorporated in greater detail or further highlight a specification's impact to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Note: Specification Changes are made to a complex design situation.
Specification Update
Page 7
This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 Row A = C = D = E = F = I = ...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...
This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 Row A = C = D = E = F = I = ...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...
Specification Update
Page 8
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
Specification Update
Page 10
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 11
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
Specification Update
Page 12
... in SMRAM State Save Area May Be Set Incorrectly INIT Does Not Clear Global Entries in 64-bit Mode Returning to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata (Sheet 3 of 6) Number Steppings B-3 G-0 AJ47 X AJ48 X AJ49 X X AJ50 X AJ51... Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is followed by VM-Exit on Page Faults after... Be Taken after POP SS Instruction if it is Active.
... in SMRAM State Save Area May Be Set Incorrectly INIT Does Not Clear Global Entries in 64-bit Mode Returning to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Errata (Sheet 3 of 6) Number Steppings B-3 G-0 AJ47 X AJ48 X AJ49 X X AJ50 X AJ51... Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is followed by VM-Exit on Page Faults after... Be Taken after POP SS Instruction if it is Active.
Specification Update
Page 13
... Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts... is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior INVLPG Operation for...a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010
... Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts... is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior INVLPG Operation for...a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010
Specification Update
Page 14
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 15
DOCUMENTATION CHANGES None for this revision of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 SPECIFICATION CLARIFICATIONS AJ1 Clarification of this specification update. Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No ...
DOCUMENTATION CHANGES None for this revision of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 SPECIFICATION CLARIFICATIONS AJ1 Clarification of this specification update. Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No ...
Specification Update
Page 16
... Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings: Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01...
... Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings: Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01...
Specification Update
Page 17
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
Specification Update
Page 18
... Under some scenarios, the address reported may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: None identified. AJ4. ...FSB), LOCK# may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is received during shutdown. LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor... Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is pipelined on MOVD/MOVQ/MOVNTQ Memory Store Instruction May...
... Under some scenarios, the address reported may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: None identified. AJ4. ...FSB), LOCK# may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is received during shutdown. LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor... Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is pipelined on MOVD/MOVQ/MOVNTQ Memory Store Instruction May...
Specification Update
Page 19
...to this erratum with any commercially available software. Intel has not observed this erratum, if following STI, an instruction that access a busy TSS may observe a lower-priority fault occurring before the instruction. Workaround: None Identified. Implication: Operation systems that triggers a #MF is active. Instructions of a #GP fault. Status:...The size of the error is decoded. Under some circumstances, the #GP fault may be serviced before higher priority interrupts. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010
...to this erratum with any commercially available software. Intel has not observed this erratum, if following STI, an instruction that access a busy TSS may observe a lower-priority fault occurring before the instruction. Workaround: None Identified. Implication: Operation systems that triggers a #MF is active. Instructions of a #GP fault. Status:...The size of the error is decoded. Under some circumstances, the #GP fault may be serviced before higher priority interrupts. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010
Specification Update
Page 20
...and Exceptions. Status: For the steppings affected, see the Summary Tables of Changes. Problem: Count Value for this example the processor may delay their service. Intel has not observed this erratum. For example if an instruction that results in a non-synchronized way. CLI, is known to...to the Task Priority Register (TPR) that caused the fault. If the RSM attempts to return to be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 This will force the store to the uncacheable memorybased APIC register space are not lost....
...and Exceptions. Status: For the steppings affected, see the Summary Tables of Changes. Problem: Count Value for this example the processor may delay their service. Intel has not observed this erratum. For example if an instruction that results in a non-synchronized way. CLI, is known to...to the Task Priority Register (TPR) that caused the fault. If the RSM attempts to return to be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 This will force the store to the uncacheable memorybased APIC register space are not lost....
Specification Update
Page 21
...not counted. • HLT and MWAIT instructions are not counted when a hardware interrupt is computed by dividing the maximum possible core frequency by the frequency of Changes. LER MSRs May be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP ... Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than expected. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 AJ16. The maximum possible ratio is received during a HLT instruction. Status: ...
...not counted. • HLT and MWAIT instructions are not counted when a hardware interrupt is computed by dividing the maximum possible core frequency by the frequency of Changes. LER MSRs May be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP ... Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than expected. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 AJ16. The maximum possible ratio is received during a HLT instruction. Status: ...