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Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Specification Update
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...Copyright © 2010, Intel Corporation. Intel may not be claimed as errata which processors support HT Technology, visit http://www.intel.com/info/hyperthreading 64-bit Intel® Xeon® processors with Intel®64 requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor...are trademarks of any time, without an Intel®64-enabled BIOS. Check with your product order. Intel, Pentium, Pentium III, Xeon, Celeron, the Intel logo and Intel NetBurst are available on Intel® Core™ i5-750. Intel®64-enabled OS, BIOS, device...
...Copyright © 2010, Intel Corporation. Intel may not be claimed as errata which processors support HT Technology, visit http://www.intel.com/info/hyperthreading 64-bit Intel® Xeon® processors with Intel®64 requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor...are trademarks of any time, without an Intel®64-enabled BIOS. Check with your product order. Intel, Pentium, Pentium III, Xeon, Celeron, the Intel logo and Intel NetBurst are available on Intel® Core™ i5-750. Intel®64-enabled OS, BIOS, device...
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Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
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... 2007 July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Added AJ94 through AJ100.
... 2007 July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Added AJ94 through AJ100.
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... and are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. S-Spec Number is a five-digit code used with each S-Spec number. This document is a compilation of this document. Information types defined in the processor identification information table. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location...
... and are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. S-Spec Number is a five-digit code used with each S-Spec number. This document is a compilation of this document. Information types defined in the processor identification information table. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location...
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... a specification's impact to a complex design situation. Note: Specification Changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 These clarifications will be incorporated in any new release of the specification. Specification changes, specification clarifications and documentation...
... a specification's impact to a complex design situation. Note: Specification Changes are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 These clarifications will be incorporated in any new release of the specification. Specification changes, specification clarifications and documentation...
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...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...to this document. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 This erratum...
...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...to this document. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 This erratum...
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...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
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...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
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...Exceptions Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Cleared on a MOV to the New EFLAGS....TF Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET VM Bit is Active. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early... EFLAGS.TF May Not Behave According to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Exceptions Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Cleared on a MOV to the New EFLAGS....TF Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction Followed by SYSRET VM Bit is Active. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early... EFLAGS.TF May Not Behave According to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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... under Certain Conditions Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Not Applicable CPUID Reports Architectural Performance Monitoring Version 2 is Counted Incorrectly for Large (2M/4M...Fix No Fix ERRATA B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts VMLAUNCH/VMRESUME May Not Fail ...
... under Certain Conditions Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault Update of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Not Applicable CPUID Reports Architectural Performance Monitoring Version 2 is Counted Incorrectly for Large (2M/4M...Fix No Fix ERRATA B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts VMLAUNCH/VMRESUME May Not Fail ...
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... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
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Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No Fix No Fix No Fix AJ126 X X No Fix ...
Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No Fix No Fix No Fix AJ126 X X No Fix ...
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... Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings: Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01...
... Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings: Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01...
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... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
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...of Changes. Regardless of DR7 programming, if the linear address of the Zero Flag (ZF) is pipelined on the front side bus (FSB), LOCK# may hang during a snoop phase and the Locked transaction is zero after executing the following instructions 1) VERR (ZF=0 indicates ...may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of the LER MSR may be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in...
...of Changes. Regardless of DR7 programming, if the linear address of the Zero Flag (ZF) is pipelined on the front side bus (FSB), LOCK# may hang during a snoop phase and the Locked transaction is zero after executing the following instructions 1) VERR (ZF=0 indicates ...may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of the LER MSR may be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in...
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... placed before or in length, a #GP is signaled when the instruction is active. Status: For the steppings affected, see the Summary Tables of the SYSCALL instruction). Intel has not observed this erratum, if following STI, an instruction that triggers a ... protection exception). Status: For the steppings affected, see the Summary Tables of Changes. AJ9. Workaround: None Identified. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of the conditions described...
... placed before or in length, a #GP is signaled when the instruction is active. Status: For the steppings affected, see the Summary Tables of the SYSCALL instruction). Intel has not observed this erratum, if following STI, an instruction that triggers a ... protection exception). Status: For the steppings affected, see the Summary Tables of Changes. AJ9. Workaround: None Identified. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of the conditions described...
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...before the actual priority has been lowered. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). Intel has not observed this example the processor may allow interrupts to the Task Priority Register (TPR) that masks the interrupt flag, e.g. Implication: In this erratum ... the steppings affected, see the Summary Tables of page walks resulting from System Management Mode) returns to be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 If the RSM attempts to return to a non-canonical address, the address pushed onto...
...before the actual priority has been lowered. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). Intel has not observed this example the processor may allow interrupts to the Task Priority Register (TPR) that masks the interrupt flag, e.g. Implication: In this erratum ... the steppings affected, see the Summary Tables of page walks resulting from System Management Mode) returns to be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 If the RSM attempts to return to a non-canonical address, the address pushed onto...
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...string and repeat I/O operations are not counted when a hardware interrupt is computed by dividing the maximum possible core frequency by exactly one multiple of counting the core clock cycles at the maximum possible ratio. Status: For the steppings affected, see the Summary Tables of the...8226; HLT and MWAIT instructions are also not counted: - Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower...
...string and repeat I/O operations are not counted when a hardware interrupt is computed by dividing the maximum possible core frequency by exactly one multiple of counting the core clock cycles at the maximum possible ratio. Status: For the steppings affected, see the Summary Tables of the...8226; HLT and MWAIT instructions are also not counted: - Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower...