Specification Update
Page 1
Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Specification Update
Page 2
... arising from published specifications. Not available on Intel® Core™ i5-750. Intel, Pentium, Pentium III, Xeon, Celeron, the Intel logo and Intel NetBurst are not intended for more information, visit http:// www.intel.com/go/virtualization Requires an Intel® HT Technology enabled system, check with an enabled Intel® processor, BIOS, virtual machine monitor (VMM). All rights...
... arising from published specifications. Not available on Intel® Core™ i5-750. Intel, Pentium, Pentium III, Xeon, Celeron, the Intel logo and Intel NetBurst are not intended for more information, visit http:// www.intel.com/go/virtualization Requires an Intel® HT Technology enabled system, check with an enabled Intel® processor, BIOS, virtual machine monitor (VMM). All rights...
Specification Update
Page 3
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Specification Update
Page 4
... July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Added AJ101 through AJ103. -006 1.0 Added AJ104 and Specification Clarification AJ1 -007 -008 -009 -010 -011 -012 -013...
... July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Added AJ101 through AJ103. -006 1.0 Added AJ104 and Specification Clarification AJ1 -007 -008 -009 -010 -011 -012 -013...
Specification Update
Page 5
...of this document. as described in other documents. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for that was not previously published. This document..., operating systems, or tools. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Hardware and software designed to identify products.
...of this document. as described in other documents. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for that was not previously published. This document..., operating systems, or tools. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Hardware and software designed to identify products.
Specification Update
Page 6
... a specification's impact to a complex design situation. Note: Specification Changes are modifications to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 These clarifications will be incorporated in any new release of the specification. Specification Clarifications describe a specification in the...
... a specification's impact to a complex design situation. Note: Specification Changes are modifications to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 These clarifications will be incorporated in any new release of the specification. Specification Clarifications describe a specification in the...
Specification Update
Page 7
...to listed stepping. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 This ...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...
...to listed stepping. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 This ...Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor...
Specification Update
Page 8
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
...; processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading Technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor...
Specification Update
Page 10
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (...When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment limit violation may... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 11
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
Specification Update
Page 12
...-Exceptions Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Set The BS Flag in DR6 May be Indicated Unless... IA32_DEBUGCTL[12] is Active. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early... Mode from SMM with Memory Types WB/WT May Lead to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...-Exceptions Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is Set The BS Flag in DR6 May be Indicated Unless... IA32_DEBUGCTL[12] is Active. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 248 May Terminate Early... Mode from SMM with Memory Types WB/WT May Lead to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 13
... Large (2M/4M) Pages May be Incorrect for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address ...Incorrect Values REP Store Instructions in a Specific Situation may cause the Processor to Hang A MOV Instruction from CR8 Register with 16 Bit ... Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to Unexpected Behavior EFLAGS, CR0, ... Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result...
... Large (2M/4M) Pages May be Incorrect for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction Address ...Incorrect Values REP Store Instructions in a Specific Situation may cause the Processor to Hang A MOV Instruction from CR8 Register with 16 Bit ... Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to Unexpected Behavior EFLAGS, CR0, ... Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could Result...
Specification Update
Page 14
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 15
... Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of this specification update. DOCUMENTATION CHANGES None for this revision of System Management Range Registers Specification Clarifications No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 SPECIFICATION CLARIFICATIONS AJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No.
... Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of this specification update. DOCUMENTATION CHANGES None for this revision of System Management Range Registers Specification Clarifications No. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 SPECIFICATION CLARIFICATIONS AJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Documentation Changes No.
Specification Update
Page 16
... Device ID register accessible through Boundary Scan. LAOTTPONO S/N The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings: Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7...
... Device ID register accessible through Boundary Scan. LAOTTPONO S/N The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following component markings: Intel® Xeon® Processor 5300 Series Identification Information (Sheet 1 of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7...
Specification Update
Page 17
... E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
Specification Update
Page 18
... is pipelined on the front side bus (FSB), LOCK# may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: None identified. Regardless of DR7 programming, if the linear address of Changes. Intel has not observed this erratum occurs, the ...value of the LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is logged in the L2 cache, the address is zero after executing the following instructions 1) VERR (ZF=0 indicates unsuccessful segment read the LER MSR before executing VERW...
... is pipelined on the front side bus (FSB), LOCK# may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: None identified. Regardless of DR7 programming, if the linear address of Changes. Intel has not observed this erratum occurs, the ...value of the LER MSR may be unexpectedly updated, if the resultant value of the Zero Flag (ZF) is logged in the L2 cache, the address is zero after executing the following instructions 1) VERR (ZF=0 indicates unsuccessful segment read the LER MSR before executing VERW...
Specification Update
Page 19
...serviced immediately after execution of greater than 15 Bytes May be serviced before the instruction. AJ7. The size of the error is active. Status: For the steppings affected, see the Summary Tables of Changes. Pending x87 FPU Exceptions (#MF) Following STI May ...while STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Thermal Monitor 1 events occur, the pending #MF may get invalid TSS fault instead of the conditions described above, while the counter is dependent on the number of occurrences of a #GP fault. Intel® Xeon® Processor 5300 Series 19...
...serviced immediately after execution of greater than 15 Bytes May be serviced before the instruction. AJ7. The size of the error is active. Status: For the steppings affected, see the Summary Tables of Changes. Pending x87 FPU Exceptions (#MF) Following STI May ...while STPCLK#, Enhanced Intel SpeedStep® Technology transitions or Thermal Monitor 1 events occur, the pending #MF may get invalid TSS fault instead of the conditions described above, while the counter is dependent on the number of occurrences of a #GP fault. Intel® Xeon® Processor 5300 Series 19...
Specification Update
Page 20
...In this erratum. This will remain pending and are serviced. Workaround: None Identified. Due to not be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: Operating systems may be serviced until the interrupt enabled flag is executed soon after... threshold interrupt before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is known to be...
...In this erratum. This will remain pending and are serviced. Workaround: None Identified. Due to not be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: Operating systems may be serviced until the interrupt enabled flag is executed soon after... threshold interrupt before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is known to be...
Specification Update
Page 21
... The extent to which this erratum occur, the value of Changes. The maximum possible ratio is determined by the bus frequency. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 LER MSRs May be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, ... counter. Implication: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than expected value in the accuracy of counting the core clock cycles at the maximum possible ratio. The value is received during HLT or MWAIT events, are not counted. Status: For ...
... The extent to which this erratum occur, the value of Changes. The maximum possible ratio is determined by the bus frequency. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 LER MSRs May be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, ... counter. Implication: The CPU_CLK_UNHALTED performance monitor with mask 1 counts a value lower than expected value in the accuracy of counting the core clock cycles at the maximum possible ratio. The value is received during HLT or MWAIT events, are not counted. Status: For ...