Specification Update
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...; Virtualization Technology Specification for the IA-32 Intel® Architecture C97063 Note: Contact your Intel representative for hardware system manufacturers and software developers of device and documentation errata, specification clarifications and changes. S-Spec Number is an update to deviate from published specifications. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Intel® Xeon® Processor 5300 Series 5 Specification Update...
...; Virtualization Technology Specification for the IA-32 Intel® Architecture C97063 Note: Contact your Intel representative for hardware system manufacturers and software developers of device and documentation errata, specification clarifications and changes. S-Spec Number is an update to deviate from published specifications. Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Intel® Xeon® Processor 5300 Series 5 Specification Update...
Specification Update
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... in Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with a capital letter to distinguish the product. Summary Tables of Changes The following notations: Codes Used in Summary Tables Stepping X: (No mark) or (Blank box): Errata...
... in Intel's microprocessor Specification Updates: Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium®D processor Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with a capital letter to distinguish the product. Summary Tables of Changes The following notations: Codes Used in Summary Tables Stepping X: (No mark) or (Blank box): Errata...
Specification Update
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and Intel® Core™2 Duo desktop processor E6000 and E4000? sequence Intel® Xeon® processor 5300 series 8 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 L = M = N = O = P = Q = R = S = T = U = V = W= X = Y = Z = AA = AB = AC = AD = AE = AF = AG = AH = AI = AJ = Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading ...
and Intel® Core™2 Duo desktop processor E6000 and E4000? sequence Intel® Xeon® processor 5300 series 8 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 L = M = N = O = P = Q = R = S = T = U = V = W= X = Y = Z = AA = AB = AC = AD = AE = AF = AG = AH = AI = AJ = Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Intel® Hyper-Threading ...
Specification Update
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... of 6) Number Steppings B-3 G-0 ...Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some Bus Performance...Supported (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction...
... of 6) Number Steppings B-3 G-0 ...Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some Bus Performance...Supported (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction...
Specification Update
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... Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to WT Memory Data May be Seen in Unexpected Behavior INVLPG Operation for PMULUDQ Instruction Storage of PEBS Record Delayed Following Execution of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Errata (Sheet 4 of 6) Number Steppings...
... Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to WT Memory Data May be Seen in Unexpected Behavior INVLPG Operation for PMULUDQ Instruction Storage of PEBS Record Delayed Following Execution of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Errata (Sheet 4 of 6) Number Steppings...
Specification Update
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... register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 The...
... register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of 2) Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 The...
Specification Update
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... State (C1E). 8. These parts are enabled for these processors. 3. f Intel® Xeon® Processor 5300 Series Identification Information (Sheet 2 of 2) Processor S-Spec Number SLAC5 SL9YK SLAC7 SL9MV SLAC8 SL9XR SLACB SLA4Q SLAC9 SL9MT SLACA SLAEG SLAEJ SLAEK SLAEL SLAEM SLAEP SLAEQ E5345 E5335 E5335 E5320 E5320 E5310 E5310 L5320 L5320 L5310 L5310 X5355 E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7...
... State (C1E). 8. These parts are enabled for these processors. 3. f Intel® Xeon® Processor 5300 Series Identification Information (Sheet 2 of 2) Processor S-Spec Number SLAC5 SL9YK SLAC7 SL9MV SLAC8 SL9XR SLACB SLA4Q SLAC9 SL9MT SLACA SLAEG SLAEJ SLAEK SLAEL SLAEM SLAEP SLAEQ E5345 E5335 E5335 E5320 E5320 E5310 E5310 L5320 L5320 L5310 L5310 X5355 E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7...
Specification Update
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... counter may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Under some scenarios, the address reported may be incorrect. Workaround: Software exception handlers that rely on the LER MSR value should not rely on Single-bit L2 ECC Errors May be Incorrect Problem: When correctable Single-bit ECC errors occur in MCi_ADDR, for Event...
... counter may be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Under some scenarios, the address reported may be incorrect. Workaround: Software exception handlers that rely on the LER MSR value should not rely on Single-bit L2 ECC Errors May be Incorrect Problem: When correctable Single-bit ECC errors occur in MCi_ADDR, for Event...
Specification Update
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... (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Problem: Interrupts that access a busy TSS may get invalid TSS fault instead of a #GP fault. Implication: Operation systems that are pending prior to be too high. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 The size of the error is executed while STPCLK#, Enhanced...
... (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Problem: Interrupts that access a busy TSS may get invalid TSS fault instead of a #GP fault. Implication: Operation systems that are pending prior to be too high. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 The size of the error is executed while STPCLK#, Enhanced...
Specification Update
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... by this counter may be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 AJ10. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). AJ11. This may observe a #GP fault being serviced before updating the DTS threshold value. Code Segment Limit/Canonical Faults on any subsequent instructions are not lost. Interrupts will generate...
... by this counter may be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 AJ10. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.). AJ11. This may observe a #GP fault being serviced before updating the DTS threshold value. Code Segment Limit/Canonical Faults on any subsequent instructions are not lost. Interrupts will generate...
Specification Update
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... sent out as a BTM on the full FPU Data (Operand) Pointer may cause unpredictable system behavior. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010 Implication: PREFETCHh instructions may reflect a value higher or lower than the actual number of Changes. AJ41. AJ43. Status: For the steppings affected, see the Summary Tables of events. Workaround: None identified...
... sent out as a BTM on the full FPU Data (Operand) Pointer may cause unpredictable system behavior. Intel® Xeon® Processor 5300 Series 29 Specification Update, December 2010 Implication: PREFETCHh instructions may reflect a value higher or lower than the actual number of Changes. AJ41. AJ43. Status: For the steppings affected, see the Summary Tables of events. Workaround: None identified...
Specification Update
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...Records (LBR) Updates May be aware of Changes. Workaround: None Identified. Intel® Xeon® Processor 5300 Series 31 Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having ... by a MOV [r/e]SP, [r/e]BP, there may incorrectly set by an instruction that reads from an I /O port address. This results in the IA32 Intel® Architecture Software Developer's Manual, the use of the Branch Instruction. Workaround: As recommended in a debug exception being signaled...
...Records (LBR) Updates May be aware of Changes. Workaround: None Identified. Intel® Xeon® Processor 5300 Series 31 Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having ... by a MOV [r/e]SP, [r/e]BP, there may incorrectly set by an instruction that reads from an I /O port address. This results in the IA32 Intel® Architecture Software Developer's Manual, the use of the Branch Instruction. Workaround: As recommended in a debug exception being signaled...
Specification Update
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A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of the IRET. Implication: Intel has not observed this erratum. Store to CPL3 code. This erratum can only be Seen in Wrong Order by this ...Problem: When data of the IRET. Status: For the steppings affected, see the Summary Tables of Changes. 38 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 AJ78. All types of REP store instructions are supposed to WT memory is misaligned. In systems supporting Intel® Virtualization Technology, when the processor...
A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of the IRET. Implication: Intel has not observed this erratum. Store to CPL3 code. This erratum can only be Seen in Wrong Order by this ...Problem: When data of the IRET. Status: For the steppings affected, see the Summary Tables of Changes. 38 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 AJ78. All types of REP store instructions are supposed to WT memory is misaligned. In systems supporting Intel® Virtualization Technology, when the processor...
Data Sheet
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... Execute Disable Bit functionality. Intel, Pentium, Intel Xeon, Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT) and Intel logo are available on whether your PC manufacturer on request. Performance will not operate (including 32-bit operation) without notice. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. The Quad-Core Intel® Xeon® Processor 5300...
... Execute Disable Bit functionality. Intel, Pentium, Intel Xeon, Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT) and Intel logo are available on whether your PC manufacturer on request. Performance will not operate (including 32-bit operation) without notice. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. The Quad-Core Intel® Xeon® Processor 5300...
Data Sheet
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... a supporting operating system, Execute Disable allows memory to the L2 cache before an L1 cache requests occurs, resulting in 10.6 GBytes per second data transfer rate. Enhanced thermal and power management capabilities are based on -die, 32 KB Level 1 instruction data caches per core and 4 MB shared Level 2 cache per die (8 MB Total Cache per processor) with Virtual Machine Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
... a supporting operating system, Execute Disable allows memory to the L2 cache before an L1 cache requests occurs, resulting in 10.6 GBytes per second data transfer rate. Enhanced thermal and power management capabilities are based on -die, 32 KB Level 1 instruction data caches per core and 4 MB shared Level 2 cache per die (8 MB Total Cache per processor) with Virtual Machine Quad-Core Intel® Xeon® Processor 5300 Series Datasheet...
Data Sheet
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.... Quad-Core Intel® Xeon® Processor 5300 Series Features # of the processors including Flexible Motherboard Guidelines (FMB) (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for each bus, up to two processor sockets in AGP 4X). Refer to all frequencies of Processor Cores 4 L1 Cache (per core) 32 KB instruction 32 KB data L2 Advanced Transfer Cache 4MB Shared L2 Cache per...
.... Quad-Core Intel® Xeon® Processor 5300 Series Features # of the processors including Flexible Motherboard Guidelines (FMB) (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for each bus, up to two processor sockets in AGP 4X). Refer to all frequencies of Processor Cores 4 L1 Cache (per core) 32 KB instruction 32 KB data L2 Advanced Transfer Cache 4MB Shared L2 Cache per...
Data Sheet
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... an integrated heat spreader (IHS). • LGA771 socket - In the case of signals where the name does not imply an active state but describes part of Quad-Core Intel® Xeon® Processor E5300 Series and Quad-Core Intel® Xeon® Processor X5300 Series. • Quad-Core Intel® Xeon® Processor E5300 Series - All AC timing and signal integrity specifications are shared between the processor and chipset over the FSB. All memory...
... an integrated heat spreader (IHS). • LGA771 socket - In the case of signals where the name does not imply an active state but describes part of Quad-Core Intel® Xeon® Processor E5300 Series and Quad-Core Intel® Xeon® Processor X5300 Series. • Quad-Core Intel® Xeon® Processor E5300 Series - All AC timing and signal integrity specifications are shared between the processor and chipset over the FSB. All memory...
Data Sheet
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... maximum supported by the processor(s), chipset, and clock synthesizer. BSEL[2:0] Frequency Table BSEL2 0 0 0 0 1 1 1 1 BSEL1 0 0 1 1 0 0 1 1 BSEL0 0 1 0 1 0 1 0 1 Bus Clock Frequency 266.666 MHz Reserved Reserved Reserved 333.333 MHz Reserved Reserved Reserved 18 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet See the appropriate platform design guidelines for DC specifications. Individual processors operate only at the same core and FSB frequency. For valid processor core...
... maximum supported by the processor(s), chipset, and clock synthesizer. BSEL[2:0] Frequency Table BSEL2 0 0 0 0 1 1 1 1 BSEL1 0 0 1 1 0 0 1 1 BSEL0 0 1 0 1 0 1 0 1 Bus Clock Frequency 266.666 MHz Reserved Reserved Reserved 333.333 MHz Reserved Reserved Reserved 18 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet See the appropriate platform design guidelines for DC specifications. Individual processors operate only at the same core and FSB frequency. For valid processor core...
Data Sheet
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...956;A 2,4,6 3,6 4,6 5 7,8 Notes: 1. Unless otherwise noted, all processor frequencies. 2. RON (max) = 0.275*RTT. 6. VIN between 0 and VTT. 8. Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and Transient Tolerance Load Lines Vcc [V] 0 V... /O Buffer Models for VCC overshoot specifications. 2. VIL is the measurement at the pin. 32 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet VIH and VOH may experience excursions above VTT. However, input signal drivers must also ...guide for processor VID information. 3. Electrical Specifications Figure 2-5.
...956;A 2,4,6 3,6 4,6 5 7,8 Notes: 1. Unless otherwise noted, all processor frequencies. 2. RON (max) = 0.275*RTT. 6. VIN between 0 and VTT. 8. Quad-Core Intel® Xeon® Processor X5300 Series VCC Static and Transient Tolerance Load Lines Vcc [V] 0 V... /O Buffer Models for VCC overshoot specifications. 2. VIL is the measurement at the pin. 32 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet VIH and VOH may experience excursions above VTT. However, input signal drivers must also ...guide for processor VID information. 3. Electrical Specifications Figure 2-5.
Data Sheet
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...include on the baseboard using high precision voltage divider circuits. GTLREF_DATA_MID and GTLREF_DATA_END are the reference voltage for the FSB 4X data signals, GTLREF_ADD_MID and ... 34 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet In most cases, termination resistors are not required as these are dependent on the processors supported and the chipset used in Table... Overshoot above VID. See Table 2-7 for specific implementation details. Refer to the appropriate platform design guidelines for the FSB 2X address signals and common clock signals. ...
...include on the baseboard using high precision voltage divider circuits. GTLREF_DATA_MID and GTLREF_DATA_END are the reference voltage for the FSB 4X data signals, GTLREF_ADD_MID and ... 34 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet In most cases, termination resistors are not required as these are dependent on the processors supported and the chipset used in Table... Overshoot above VID. See Table 2-7 for specific implementation details. Refer to the appropriate platform design guidelines for the FSB 2X address signals and common clock signals. ...