Operating Guide
Page 2
...,A*LT -M,%. Includes an adjacent KCC (Korean Communications Commission) certification number: KCC-REM-CPU-DQ87PG. PCI Connector B. Serial Port Connector HH. On/Off +5 V - The purpose of the BIOS is competely seated in cards to make changes to : http://www.intel.com/support/motherboards/desktop/sb/CS-022312.htm. There are various methods of Communications Compliance...
...,A*LT -M,%. Includes an adjacent KCC (Korean Communications Commission) certification number: KCC-REM-CPU-DQ87PG. PCI Connector B. Serial Port Connector HH. On/Off +5 V - The purpose of the BIOS is competely seated in cards to make changes to : http://www.intel.com/support/motherboards/desktop/sb/CS-022312.htm. There are various methods of Communications Compliance...
Product Specification
Page 69
... the PCI auto-configuration utility, LAN EEPROM information, and Plug and Play support. The initial production BIOSs are identified as PGQ8710H.86A. When the BIOS Setup configuration jumper is powered-up, the BIOS compares the CPU version and the microcode version in the Serial Peripheral Interface Flash Memory (SPI ... program can be used to configure mode and the computer is set to view and change the BIOS settings for the computer. Intel Visual BIOS Screen 69 Figure 18. The BIOS displays a message during POST identifying the type of BIOS Features 3.1 Introduction The board uses ...
... the PCI auto-configuration utility, LAN EEPROM information, and Plug and Play support. The initial production BIOSs are identified as PGQ8710H.86A. When the BIOS Setup configuration jumper is powered-up, the BIOS compares the CPU version and the microcode version in the Serial Peripheral Interface Flash Memory (SPI ... program can be used to configure mode and the computer is set to view and change the BIOS settings for the computer. Intel Visual BIOS Screen 69 Figure 18. The BIOS displays a message during POST identifying the type of BIOS Features 3.1 Introduction The board uses ...
Product Specification
Page 85
... APs 0x46 End CPU SMM Init CPU DXE Phase 0x47 CPU DXE Phase begin 0x48 Refresh memory space attributes according to MTRRs 0x49 Load the microcode if needed 0x4A 0x4B Initialize strings to HII database Initialize MP Support 0x4C 0x4D CPU DXE Phase End CPU DXE SMM Phase CPU DXE SMM Phase ...begin 0x4E Relocate SM bases for all APs 0x4F CPU DXE SMM Phase end IO BUSES 0x50 Enumerating PCI buses 0x51 Allocating resources...
... APs 0x46 End CPU SMM Init CPU DXE Phase 0x47 CPU DXE Phase begin 0x48 Refresh memory space attributes according to MTRRs 0x49 Load the microcode if needed 0x4A 0x4B Initialize strings to HII database Initialize MP Support 0x4C 0x4D CPU DXE Phase End CPU DXE SMM Phase CPU DXE SMM Phase ...begin 0x4E Relocate SM bases for all APs 0x4F CPU DXE SMM Phase end IO BUSES 0x50 Enumerating PCI buses 0x51 Allocating resources...