Aspire X1200 / X3200 Service Guide
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... POST Routine Description Test CMOS R/W functionality Early chipset initialization T Disable shadow RAM T Disable L2 cache (socket 7 or below) T Program basic chipset registers Detect memory T Auto-detection of DRAM size, type, and ECC T Auto-detection of L2 cache (socket 7 or below) Expand compressed BIOS code ... or actions in the sequence shown in FRU/Action column, if the FRU replacement does not solve the problem, put the original part back in physical address 1000:0 Reserved Initial Superio_Earl_Init switch Reserved 1 Blank out screen 2 Clear CMOS error flag Reserved 1 Clear 8042...
... POST Routine Description Test CMOS R/W functionality Early chipset initialization T Disable shadow RAM T Disable L2 cache (socket 7 or below) T Program basic chipset registers Detect memory T Auto-detection of DRAM size, type, and ECC T Auto-detection of L2 cache (socket 7 or below) Expand compressed BIOS code ... or actions in the sequence shown in FRU/Action column, if the FRU replacement does not solve the problem, put the original part back in physical address 1000:0 Reserved Initial Superio_Earl_Init switch Reserved 1 Blank out screen 2 Clear CMOS error flag Reserved 1 Clear 8042...