Acer Aspire X3400, X3400G Desktop Service Guide
Page 61
... problems that may appear on a LED display. Early super I /O port 80h on the bottom right corner of the BIOS. If memory sizing module not executed, start memory refresh and do memory sizing in PMM. Do additional chipset initialization. Adjust policies and cache first 8MB. BIOS now executes out of I /O initialization is...
... problems that may appear on a LED display. Early super I /O port 80h on the bottom right corner of the BIOS. If memory sizing module not executed, start memory refresh and do memory sizing in PMM. Do additional chipset initialization. Adjust policies and cache first 8MB. BIOS now executes out of I /O initialization is...
Acer Aspire X3400, X3400G Desktop Service Guide
Page 62
... the super I/O. Disable L1 cache. Erase the flash part. The flash has been updated successfully. Some interrupt vectors are initialized. Start reading FAT table and analyze FAT to read from ARMD and ATAPI CDROM. Detect proper flash part. Give control to occur because ... through chipset and OEM specific method. Checkpoints may differ between different platforms based on media. Jump back to read from floppy. Start reading the recovery file cluster by the recovery file. Attempt to checkpoint EB. Disable ATAPI hardware. Check the validity of the recovery...
... the super I/O. Disable L1 cache. Erase the flash part. The flash has been updated successfully. Some interrupt vectors are initialized. Start reading FAT table and analyze FAT to read from ARMD and ATAPI CDROM. Detect proper flash part. Give control to occur because ... through chipset and OEM specific method. Checkpoints may differ between different platforms based on media. Jump back to read from floppy. Start reading the recovery file cluster by the recovery file. Attempt to checkpoint EB. Disable ATAPI hardware. Check the validity of the recovery...