Aspire T300 Service Guide
Page 16
...64MB~2G Cache Memory Item First-Level Cache Configurations Cache function control Second-Level Cache Configurations L2 Cache RAM type L2 Cache RAM size L2 Cache RAM speed L2 Cache RAM voltage L2 Cache function control L2 Cache scheme Specification Enable/Disable by BIOS Setup PBSRAM 512-KB One...possible combinations of memory module. System Memory Item Memory socket number Support memory size per socket Support maximum memory size Support memory type Support memory speed Support memory voltage Support memory module package Support to parity check feature Support to Error Correction Code (ECC) ...
...64MB~2G Cache Memory Item First-Level Cache Configurations Cache function control Second-Level Cache Configurations L2 Cache RAM type L2 Cache RAM size L2 Cache RAM speed L2 Cache RAM voltage L2 Cache function control L2 Cache scheme Specification Enable/Disable by BIOS Setup PBSRAM 512-KB One...possible combinations of memory module. System Memory Item Memory socket number Support memory size per socket Support maximum memory size Support memory type Support memory speed Support memory voltage Support memory module package Support to parity check feature Support to Error Correction Code (ECC) ...
Aspire T300 Service Guide
Page 57
...Acer common tasks carried out by a port & interface swap (optional) 3. Blank out screen 2. Enable keyboard interface Reserved 1. keep beeping the speaker. POST Check Points When POST executes a task, it uses a series of L2 cache (socket 7 or below ) • Program basic chipset registers Detect memory • Auto-detection of DRAM size, type... 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Description Test CMOS R/W functionality Early chipset initialization: • Disable shadow RAM • Disable L2 Cache (socket 7 or below ) Expand compressed BIOS code to DRAM Call chipset hook to copy ...
...Acer common tasks carried out by a port & interface swap (optional) 3. Blank out screen 2. Enable keyboard interface Reserved 1. keep beeping the speaker. POST Check Points When POST executes a task, it uses a series of L2 cache (socket 7 or below ) • Program basic chipset registers Detect memory • Auto-detection of DRAM size, type... 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Description Test CMOS R/W functionality Early chipset initialization: • Disable shadow RAM • Disable L2 Cache (socket 7 or below ) Expand compressed BIOS code to DRAM Call chipset hook to copy ...
Aspire T300/APSV Service Guide
Page 16
...64MB~2G Cache Memory Item First-Level Cache Configurations Cache function control Second-Level Cache Configurations L2 Cache RAM type L2 Cache RAM size L2 Cache RAM speed L2 Cache RAM voltage L2 Cache function control L2 Cache scheme Specification Enable/Disable by BIOS Setup PBSRAM 512-KB One...and its supported display modes. System Memory Item Memory socket number Support memory size per socket Support maximum memory size Support memory type Support memory speed Support memory voltage Support memory module package Support to parity check feature Support to Error Correction Code (ECC) feature...
...64MB~2G Cache Memory Item First-Level Cache Configurations Cache function control Second-Level Cache Configurations L2 Cache RAM type L2 Cache RAM size L2 Cache RAM speed L2 Cache RAM voltage L2 Cache function control L2 Cache scheme Specification Enable/Disable by BIOS Setup PBSRAM 512-KB One...and its supported display modes. System Memory Item Memory socket number Support memory size per socket Support maximum memory size Support memory type Support memory speed Support memory voltage Support memory module package Support to parity check feature Support to Error Correction Code (ECC) feature...
Aspire T300/APSV Service Guide
Page 57
...8226; Program basic chipset registers Detect memory • Auto-detection of DRAM size, type and ECC. • Auto-detection of preset numbers called check point to E000 & F000 shadow RAM Expand the Xgroup codes locating in physical address 1000:0 Reserved Initial Superio_Early_Init switch Reserved 1..../O chips 2. keep beeping the speaker. Clear CMOS error flag Reserved 1. If test fails. Reserved Chapter 4 51 The following table describes the Acer common tasks carried out by a port & interface swap (optional) 3. Clear 8042 interface 2. Initialize 8042 self-test 1. Blank out screen 2....
...8226; Program basic chipset registers Detect memory • Auto-detection of DRAM size, type and ECC. • Auto-detection of preset numbers called check point to E000 & F000 shadow RAM Expand the Xgroup codes locating in physical address 1000:0 Reserved Initial Superio_Early_Init switch Reserved 1..../O chips 2. keep beeping the speaker. Clear CMOS error flag Reserved 1. If test fails. Reserved Chapter 4 51 The following table describes the Acer common tasks carried out by a port & interface swap (optional) 3. Clear 8042 interface 2. Initialize 8042 self-test 1. Blank out screen 2....