Acer Altos G301 User's Guide
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Contents 1 Getting started 1 Overview 3 Processor 3 Memory 4 System chipsets 4 ServerWorks GC-SL chipset 4 LAN subsystem 4 Expansion slots 5 PCI bus 5 Hardware management support 5 Features summary 6 Preinstallation requirements 7 Selecting a site 7 Checking the package contents 7 ...
Contents 1 Getting started 1 Overview 3 Processor 3 Memory 4 System chipsets 4 ServerWorks GC-SL chipset 4 LAN subsystem 4 Expansion slots 5 PCI bus 5 Hardware management support 5 Features summary 6 Preinstallation requirements 7 Selecting a site 7 Checking the package contents 7 ...
Acer Altos G301 User's Guide
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... storage device 36 Installing a hard disk 38 Installing a DLT 39 Installing and removing the CPU 40 Installing a CPU 40 Removing a CPU 41 Installing and removing memory modules 43 Reconfiguring the system 44 Installing expansion cards 45 4 Setup utility 47 Introduction 49 Setup Menu 50 Setup submenu: Main 51 Setup submenu: Advanced...
... storage device 36 Installing a hard disk 38 Installing a DLT 39 Installing and removing the CPU 40 Installing a CPU 40 Removing a CPU 41 Installing and removing memory modules 43 Reconfiguring the system 44 Installing expansion cards 45 4 Setup utility 47 Introduction 49 Setup Menu 50 Setup submenu: Main 51 Setup submenu: Advanced...
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...Pipelined Technology, Advanced Dynamic Execution, Enhanced Floating-Point and Multimedia Unit, Streaming SIMD Extensions 2 (SSE2) Instructions. 3 Overview The Acer Altos G301 is fully compatible with the ServerWorks GC-SL chipset. The system is a PCI bus based single processor system board built on ... 7.3/8.0, Windows NT 4.0 server, and Windows 2000 server. For expandability, the system board using ATI Rage XL integrated with 8MB memory, one Pentium 4 processor supporting frequencies start at 1.8GHz. This system board supports 400/533MHz system bus frequencies for video output....
...Pipelined Technology, Advanced Dynamic Execution, Enhanced Floating-Point and Multimedia Unit, Streaming SIMD Extensions 2 (SSE2) Instructions. 3 Overview The Acer Altos G301 is fully compatible with the ServerWorks GC-SL chipset. The system is a PCI bus based single processor system board built on ... 7.3/8.0, Windows NT 4.0 server, and Windows 2000 server. For expandability, the system board using ATI Rage XL integrated with 8MB memory, one Pentium 4 processor supporting frequencies start at 1.8GHz. This system board supports 400/533MHz system bus frequencies for video output....
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...DDR SDRAM (Synchronous DRAM) DIMMs. For data integrity, the default setting of the ECC (errorcorrecting code) function of the memory system in features include main memory interface with optimized support for DDR SDRAM, 64-bit, 33MHz primary PCI bus interface (PCI) with integrated PCI arbiter,..., and PC 2001 compliance. LAN subsystem Another cost-effective feature for network solution is enabled. 4 1 Getting started Memory The four DIMM sockets on board allow memory upgrade to meet the needs of high performance systems. It consists of two components: SeverWorks CMIC-SL (North bridge)...
...DDR SDRAM (Synchronous DRAM) DIMMs. For data integrity, the default setting of the ECC (errorcorrecting code) function of the memory system in features include main memory interface with optimized support for DDR SDRAM, 64-bit, 33MHz primary PCI bus interface (PCI) with integrated PCI arbiter,..., and PC 2001 compliance. LAN subsystem Another cost-effective feature for network solution is enabled. 4 1 Getting started Memory The four DIMM sockets on board allow memory upgrade to meet the needs of high performance systems. It consists of two components: SeverWorks CMIC-SL (North bridge)...
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... • Onboard Gigabit Ethernet chip that supports WOL and AOL • Four DIMM sockets that accept 128-, 256-, 512-, and 1-GB DDR SDRAMs with a maximum memory upgrade of 4-GB • On-board ATI Rage XL and 5 PCI bus slots with 4 supporting 64-bit PCI • System clock/calendar with battery backup...
... • Onboard Gigabit Ethernet chip that supports WOL and AOL • Four DIMM sockets that accept 128-, 256-, 512-, and 1-GB DDR SDRAMs with a maximum memory upgrade of 4-GB • On-board ATI Rage XL and 5 PCI bus slots with 4 supporting 64-bit PCI • System clock/calendar with battery backup...
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...socket is slotted to form different configurations. This independence allows you to install DIMMs with different capacities to ensure proper installation. 43 Installing and removing memory modules The four 184-pin sockets onboard support DDR SDRAM-type DIMMs. You may have inserted it does not completely fit, you may install ...128-MB, 256-MB, 512-MB, or 1-GB DIMMs for a maximum of 4-GB system memory. To install a DIMM, align it to an empty slot and press it in until the holding clips secure the DIMM in a DIMM but it the...
...socket is slotted to form different configurations. This independence allows you to install DIMMs with different capacities to ensure proper installation. 43 Installing and removing memory modules The four 184-pin sockets onboard support DDR SDRAM-type DIMMs. You may have inserted it does not completely fit, you may install ...128-MB, 256-MB, 512-MB, or 1-GB DIMMs for a maximum of 4-GB system memory. To install a DIMM, align it to an empty slot and press it in until the holding clips secure the DIMM in a DIMM but it the...
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Note: Place your system To remove a DIMM, press the holding clips to gently disengage the DIMM from the socket. 44 3 Upgrading your forefingers on the top of the DIMM before you press the holding clips on both sides of the socket outward to release the DIMM. Run Setup to view the new value for total system memory and make a note of memory installed. Reconfiguring the system The system automatically detects the amount of it.
Note: Place your system To remove a DIMM, press the holding clips to gently disengage the DIMM from the socket. 44 3 Upgrading your forefingers on the top of the DIMM before you press the holding clips on both sides of the socket outward to release the DIMM. Run Setup to view the new value for total system memory and make a note of memory installed. Reconfiguring the system The system automatically detects the amount of it.
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... the system RAM. In this case, the system cannot retain configuration values in CMOS. The Setup program loads configuration values into the battery-backed nonvolatile memory called CMOS RAM. Note: If you get a Run Setup message. Ask a qualified technician for assistance. The system reboots immediately after you have saved all open... you repeatedly receive Run Setup messages, the battery may be bad. 49 Introduction Most systems are already configured by the manufacturer or the dealer. This memory area is no need to run Setup, make sure that you exit Setup.
... the system RAM. In this case, the system cannot retain configuration values in CMOS. The Setup program loads configuration values into the battery-backed nonvolatile memory called CMOS RAM. Note: If you get a Run Setup message. Ask a qualified technician for assistance. The system reboots immediately after you have saved all open... you repeatedly receive Run Setup messages, the battery may be bad. 49 Introduction Most systems are already configured by the manufacturer or the dealer. This memory area is no need to run Setup, make sure that you exit Setup.
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... Port IRQ Use this item to determine the IRQ of the parallel port. • Parallel Port Mode Select Use this item to allocate DMA (Direct Memory Access) channel for the parallel port.
... Port IRQ Use this item to determine the IRQ of the parallel port. • Parallel Port Mode Select Use this item to allocate DMA (Direct Memory Access) channel for the parallel port.
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... No system boot if this item is enabled. This allows user to see the detail N/A BIOS and IPMI event. Memory DIMM might be disabled by memory reduction feature. 64 4 Setup utility Parameter PCI Device Event Logging Intrusion Event logging Clear Intrusion Status Clear All Event Logs... Reset Disabled Memory Bank View Event Log Description Options Allow/Not allow logging of PCI PERR error events. Enable all memory banks on next boot. Allow/Not allow logging of chassis intrusion events.
... No system boot if this item is enabled. This allows user to see the detail N/A BIOS and IPMI event. Memory DIMM might be disabled by memory reduction feature. 64 4 Setup utility Parameter PCI Device Event Logging Intrusion Event logging Clear Intrusion Status Clear All Event Logs... Reset Disabled Memory Bank View Event Log Description Options Allow/Not allow logging of PCI PERR error events. Enable all memory banks on next boot. Allow/Not allow logging of chassis intrusion events.
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... or other kinds of low-performance components. Auto Configuration with slower memory chips or other kinds of low-performance components. Press the Y key to indicate Yes, and then press Enter to install fail-safe settings for all ...
... or other kinds of low-performance components. Auto Configuration with slower memory chips or other kinds of low-performance components. Press the Y key to indicate Yes, and then press Enter to install fail-safe settings for all ...
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... verified. D1h Initializing the DMA controller, performing the keyboard controller BAT test, starting . Otherwise, going to real mode. D3h Starting memory sizing next. Next, checking if was pressed or the system BIOS checksum is disabled. Executing any OEM patches and setting the stack next...Next, the initialization code checksum will go to the uncompressed code in shadow RAM at E000:0000h. The initialization code is starting memory refresh, and entering 4 GB flat mode next. D4h Returning to checkpoint code D7h. D6h Control is in order of execution: ...
... verified. D1h Initializing the DMA controller, performing the keyboard controller BAT test, starting . Otherwise, going to real mode. D3h Starting memory sizing next. Next, checking if was pressed or the system BIOS checksum is disabled. Executing any OEM patches and setting the stack next...Next, the initialization code checksum will go to the uncompressed code in shadow RAM at E000:0000h. The initialization code is starting memory refresh, and entering 4 GB flat mode next. D4h Returning to checkpoint code D7h. D6h Control is in order of execution: ...
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... The AMIBOOT.ROM file is not in drive A:. F5h Next, disabling internal cache memory. FBh Next, detecting the type of the diskette. Next, beginning the base 512 KB memory test. E1h Initializing the interrupt vector table next. Edh Initializing the floppy drive. ...AMIBIOS POST Checkpoint Codes POST Checkpoint Codes Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in drive A:. Enabling internal cache memory. F0h Next, searching for a floppy diskette in the root directory. F2h Next, reading and analyzing the floppy diskette FAT to ...
... The AMIBOOT.ROM file is not in drive A:. F5h Next, disabling internal cache memory. FBh Next, detecting the type of the diskette. Next, beginning the base 512 KB memory test. E1h Initializing the interrupt vector table next. Edh Initializing the floppy drive. ...AMIBIOS POST Checkpoint Codes POST Checkpoint Codes Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in drive A:. Enabling internal cache memory. F0h Next, searching for a floppy diskette in the root directory. F2h Next, reading and analyzing the floppy diskette FAT to ...
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... flash ROM. Next, performing any required initialization before the keyboard BAT command is issued. 0Ch The keyboard controller input buffer is disabled. Next, disabling cache memory. 06h Uncompressing the POST code next. 07h Next, initializing the CPU and the CPU data area. 08h The CMOS checksum calculation is done next. 0Ah...
... flash ROM. Next, performing any required initialization before the keyboard BAT command is issued. 0Ch The keyboard controller input buffer is disabled. Next, disabling cache memory. 06h Uncompressing the POST code next. 07h Next, initializing the CPU and the CPU data area. 08h The CMOS checksum calculation is done next. 0Ah...
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Next, initializing the chipset. 14h The 8254 timer test will begin . Starting the memory refresh test next. 1Ah The memory refresh line is over. Next, issuing the Pin 23 and 24 blocking and unblocking command. 11h Next, checking if or keys were pressed during power ...
Next, initializing the chipset. 14h The 8254 timer test will begin . Starting the memory refresh test next. 1Ah The memory refresh line is over. Next, issuing the Pin 23 and 24 blocking and unblocking command. 11h Next, checking if or keys were pressed during power ...
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...control to perform any required processing after the video ROM had control. 2Eh Completed post-video ROM test processing. The display memory read/write test is done. 125 Checkpoint Code Description 25h Interrupt vector initialization is complete. Looking for alternate display retrace checking... next. 34h Video display checking is not found, performing the display memory read /write test passed. Look for additional information. 2Bh Passing control to the video ROM to the video ROM is about...
...control to perform any required processing after the video ROM had control. 2Eh Completed post-video ROM test processing. The display memory read/write test is done. 125 Checkpoint Code Description 25h Interrupt vector initialization is complete. Looking for alternate display retrace checking... next. 34h Video display checking is not found, performing the display memory read /write test passed. Look for additional information. 2Bh Passing control to the video ROM to the video ROM is about...
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...Displaying the power on . See page 131 for the memory test next. 43h Entered protected mode. The protected mode memory test is about to the base 640 KB memory next. 48h Patterns written in base memory. Checking for additional information. 39h Displaying bus initialization error...42h The descriptor tables are prepared. Memory size calculation has been done. Writing patterns to test memory next. 47h The memory pattern has been written to check memory wraparound at 0:0 and finding the total system memory size next. 46h The memory wraparound test is on message next....
...Displaying the power on . See page 131 for the memory test next. 43h Entered protected mode. The protected mode memory test is about to the base 640 KB memory next. 48h Patterns written in base memory. Checking for additional information. 39h Displaying bus initialization error...42h The descriptor tables are prepared. Memory size calculation has been done. Writing patterns to test memory next. 47h The memory pattern has been written to check memory wraparound at 0:0 and finding the total system memory size next. 46h The memory wraparound test is on message next....
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... was successful. If this is a power on situation, going to checkpoint 52h next. 4Eh The memory test started . Clearing the memory above 1 MB next. 4Dh The memory above 1 MB has been cleared via a soft reset. Saving the memory size next. Disabling the Gate A20 line, parity, and the NMI next. Going to checkpoint 4Eh...
... was successful. If this is a power on situation, going to checkpoint 52h next. 4Eh The memory test started . Clearing the memory above 1 MB next. 4Dh The memory above 1 MB has been cleared via a soft reset. Saving the memory size next. Disabling the Gate A20 line, parity, and the NMI next. Going to checkpoint 4Eh...
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... next. 128 Appendix A: AMIBIOS POST Checkpoint Codes Checkpoint Code Description 57h The A20 address line, parity, and the NMI are disabled. Adjusting the memory size depending on relocation and shadowing next. 58h The memory size was adjusted for relocation and shadowing. Clearing the Hit message next. 59h The Hit message is cleared.
... next. 128 Appendix A: AMIBIOS POST Checkpoint Codes Checkpoint Code Description 57h The A20 address line, parity, and the NMI are disabled. Adjusting the memory size depending on relocation and shadowing next. 58h The memory size was adjusted for relocation and shadowing. Clearing the Hit message next. 59h The Hit message is cleared.
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... required programming before WINBIOS Setup next. 87h The programming before passing control to the adaptor ROM at C800. Checking for a memory size mismatch with CMOS RAM data next. 85h The memory size check is displayed. Displaying the power on screen message next. 8Bh The first screen message has been displayed. Uncompressing the...
... required programming before WINBIOS Setup next. 87h The programming before passing control to the adaptor ROM at C800. Checking for a memory size mismatch with CMOS RAM data next. 85h The memory size check is displayed. Displaying the power on screen message next. 8Bh The first screen message has been displayed. Uncompressing the...