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...) and, for conflicts or incompatibilities arising from published specifications. Setup requires configuration by the Trusted Computing Group and specific software for some uses, certain computer system software enabled for Intel® 64 architecture. For more information including details ...differentiate features within each processor family, not across different processor families. Intel® Active Management Technology requires the computer system to specifications and product descriptions at http://www.intel.com. With regard to contain a TPM v1.2, as connection with...
...) and, for conflicts or incompatibilities arising from published specifications. Setup requires configuration by the Trusted Computing Group and specific software for some uses, certain computer system software enabled for Intel® 64 architecture. For more information including details ...differentiate features within each processor family, not across different processor families. Intel® Active Management Technology requires the computer system to specifications and product descriptions at http://www.intel.com. With regard to contain a TPM v1.2, as connection with...
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Contents Contents Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 14 Errata ...17 Specification Changes 49 Specification Clarifications 50 Documentation Changes 51 § 3 Specification Update
Contents Contents Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 14 Errata ...17 Specification Changes 49 Specification Clarifications 50 Documentation Changes 51 § 3 Specification Update
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...; Core™ i5-680 processor. Added Errata AAU98-AAU102 Erratum AAU32 added to include the SKU information for the Intel® Core™ i3-560 processor. Updated Processor Identification table to this specification Update in Component Identification table. Added Errataum AAU92. Corrected Extended Model and Model Number register values in error; Date January...
...; Core™ i5-680 processor. Added Errata AAU98-AAU102 Erratum AAU32 added to include the SKU information for the Intel® Core™ i3-560 processor. Updated Processor Identification table to this specification Update in Component Identification table. Added Errataum AAU92. Corrected Extended Model and Model Number register values in error; Date January...
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... Nomenclature are consolidated into the specification update and are no longer published in the Affected Documents table below. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and...
... Nomenclature are consolidated into the specification update and are no longer published in the Affected Documents table below. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and...
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... situation. These changes will be used to identify products. These clarifications will be incorporated in any new release of the specification. Under these circumstances, errata removed from published specifications. Specification Clarifications describe a specification in the specification update throughout the product's lifecycle, or until a particular stepping is a five-digit code used with each S-Spec number. Products...
... situation. These changes will be used to identify products. These clarifications will be incorporated in any new release of the specification. Under these circumstances, errata removed from published specifications. Specification Clarifications describe a specification in the specification update throughout the product's lifecycle, or until a particular stepping is a five-digit code used with each S-Spec number. Products...
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...in a future stepping of a table row indicates this erratum is fixed in listed stepping or specification change or update will be fixed in a future stepping of the document. 8 Specification Update Intel may be implemented. Status Doc: Plan Fix: Fixed: No Fix: Document change does not... apply to left of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses ...
...in a future stepping of a table row indicates this erratum is fixed in listed stepping or specification change or update will be fixed in a future stepping of the document. 8 Specification Update Intel may be implemented. Status Doc: Plan Fix: Fixed: No Fix: Document change does not... apply to left of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses ...
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... MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting During On-Demand TM1 9 Specification Update
... MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting During On-Demand TM1 9 Specification Update
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...Cause an Unexpected Interrupt xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in error; all erratum details removed from the specification update document. Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack Infinite Stream of Interrupts... While EPT is Disable Memory Aliasing of IA32_APERF/IA32_MPERF Counters on EPT-Induced VM Exits after a Translation Change Back to this specification Update in Periodic Mode Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Changing the Memory ...
...Cause an Unexpected Interrupt xAPIC Timer May Decrement Too Quickly Following an Automatic Reload While in error; all erratum details removed from the specification update document. Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack Infinite Stream of Interrupts... While EPT is Disable Memory Aliasing of IA32_APERF/IA32_MPERF Counters on EPT-Induced VM Exits after a Translation Change Back to this specification Update in Periodic Mode Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Changing the Memory ...
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... The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors Occurring on Both Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core...
... The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors Occurring on Both Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core...
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...to Processor Livelock Processor Hangs on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to this specification Update in the Presence of a Core PCIe Port's LTSSM May Not Transition Properly in error; all erratum details removed from the... specification update document. Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over-Counted VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL...
...to Processor Livelock Processor Hangs on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to this specification Update in the Presence of a Core PCIe Port's LTSSM May Not Transition Properly in error; all erratum details removed from the... specification update document. Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over-Counted VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL...
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Documentation Changes Number DOCUMENTATION CHANGES None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS None for this revision of this specification update. Errata (Sheet 5 of 5) Number AAU104 Steppings C-2 K-0 X X Status No Fix ...Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior Execution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer is Invalid PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Specification Changes Number SPECIFICATION...
Documentation Changes Number DOCUMENTATION CHANGES None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS None for this revision of this specification update. Errata (Sheet 5 of 5) Number AAU104 Steppings C-2 K-0 X X Status No Fix ...Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior Execution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer is Invalid PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Specification Changes Number SPECIFICATION...
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... 1 in the EAX register. See Table 1 for the processor stepping ID number in the PCI function 0 configuration space. 14 Specification Update Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after reset is executed with the Family...the Device ID register accessible through Boundary Scan. Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register ...
... 1 in the EAX register. See Table 1 for the processor stepping ID number in the PCI function 0 configuration space. 14 Specification Update Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after reset is executed with the Family...the Device ID register accessible through Boundary Scan. Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register ...
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... 3.33 / 1333 / 733 SLBXL i5-655K K-0 20655h 3.20 / 1333 / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73...
... 3.33 / 1333 / 733 SLBXL i5-655K K-0 20655h 3.20 / 1333 / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73...
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...brand string.) 16 Specification Update Core frequency of 87 W. 10. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled. 6. Intel® Trusted Execution Technology (Intel® TXT) enabled... Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB...
...brand string.) 16 Specification Update Core frequency of 87 W. 10. Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled. 6. Intel® Trusted Execution Technology (Intel® TXT) enabled... Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB...
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..., as fast strings. of Changes. Implication: Upon crossing the page boundary the following may get invalid TSS fault instead of Changes. 17 Specification Update REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead...May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may be 8 bytes, as described in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as opposed to UC/WP/WT memory types, may start using an...
..., as fast strings. of Changes. Implication: Upon crossing the page boundary the following may get invalid TSS fault instead of Changes. 17 Specification Update REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead...May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may be 8 bytes, as described in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as opposed to UC/WP/WT memory types, may start using an...
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...due to 0, or a DNA exception pending. Status: For the steppings affected, see the Summary Tables of the side- effect. Intel has not observed this behavior by the exception handler. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter ... #GP (General Protection Exception) fault is no impact from memory that instruction by using simple integer-based load instructions when 18 Specification Update Workaround: None identified. Particularly, while CR0.TS [bit 3] is used to write back memory there is generated after all...
...due to 0, or a DNA exception pending. Status: For the steppings affected, see the Summary Tables of the side- effect. Intel has not observed this behavior by the exception handler. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter ... #GP (General Protection Exception) fault is no impact from memory that instruction by using simple integer-based load instructions when 18 Specification Update Workaround: None identified. Particularly, while CR0.TS [bit 3] is used to write back memory there is generated after all...
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... will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. Implication: The value of Changes. 19 Specification Update For the steppings affected, see the Summary Tables of the LBR, BTS, and BTM immediately after an Exit from SMM Problem: After a return from...
... will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. Implication: The value of Changes. 19 Specification Update For the steppings affected, see the Summary Tables of the LBR, BTS, and BTM immediately after an Exit from SMM Problem: After a return from...
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Intel has not observed this erratum occurs, #DB will be mishandled. Implication: In IA-32e mode, under Certain Conditions May Cause an Unexpected Alignment Check Exception .... Implication: When this erratum on the IRET instruction even though alignment checks were disabled at the start of Changes. 20 Specification Update Fault on ENTER Instruction May Result in IA-32 Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for use with Floating Point Exception Pending May Be Mishandled Problem: In...
Intel has not observed this erratum occurs, #DB will be mishandled. Implication: In IA-32e mode, under Certain Conditions May Cause an Unexpected Alignment Check Exception .... Implication: When this erratum on the IRET instruction even though alignment checks were disabled at the start of Changes. 20 Specification Update Fault on ENTER Instruction May Result in IA-32 Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for use with Floating Point Exception Pending May Be Mishandled Problem: In...
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... not be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of a #GP fault. Status: For the steppings affected, see the Summary Tables ...extended to this erratum, the Overflow bit in length can incorrectly set the Overflow (bit [62]) in the event of Changes. 21 Specification Update Status: For the steppings affected, see the Summary Tables of an exception/ interrupt. Implication: LBR, BTS and BTM may not ...
... not be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of a #GP fault. Status: For the steppings affected, see the Summary Tables ...extended to this erratum, the Overflow bit in length can incorrectly set the Overflow (bit [62]) in the event of Changes. 21 Specification Update Status: For the steppings affected, see the Summary Tables of an exception/ interrupt. Implication: LBR, BTS and BTM may not ...
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... steppings affected, see the Summary Tables of the CS segment register will provide erroneous results. Intel has not observed this erratum with any commercially-available software. Implication: The corruption of the bottom two bits of Changes. 22 Specification Update Implication: When this erratum with any commercially-available software. Corruption of Changes. Implication...
... steppings affected, see the Summary Tables of the CS segment register will provide erroneous results. Intel has not observed this erratum with any commercially-available software. Implication: The corruption of the bottom two bits of Changes. 22 Specification Update Implication: When this erratum with any commercially-available software. Corruption of Changes. Implication...