Specifications
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... or its subsidiaries in clock, speed, cache, or other benefits will vary depending on Intel architecture requires a computer system with Intel Turbo Boost Technology capability. For more information. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are referenced in this document, or other countries. *Other names and brands may be compatible with...
... or its subsidiaries in clock, speed, cache, or other benefits will vary depending on Intel architecture requires a computer system with Intel Turbo Boost Technology capability. For more information. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are referenced in this document, or other countries. *Other names and brands may be compatible with...
Specifications
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.... AAU97 -007 -008 -009 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-680 processor. Added Errata AAU88-AAU91. all erratum details removed from the specification update...
.... AAU97 -007 -008 -009 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-680 processor. Added Errata AAU88-AAU91. all erratum details removed from the specification update...
Specifications
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... is a compilation of applications, operating systems, or tools. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006...
... is a compilation of applications, operating systems, or tools. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006...
Specifications
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... given stepping must assume that all errata documented for that stepping are present on all notes associated with any new release of the specification. as , core speed, L2 cache size, package type, etc. Nomenclature Errata are differentiated by their unique characteristics such as described in the processor identification information table.
... given stepping must assume that all errata documented for that stepping are present on all notes associated with any new release of the specification. as , core speed, L2 cache size, package type, etc. Nomenclature Errata are differentiated by their unique characteristics such as described in the processor identification information table.
Specifications
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...IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Disable Memory Aliasing of Code Pages May Cause Unpredictable ... Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected Sleeping Cores May Not be Counted While EPT is Pending May Cause an Unexpected Interrupt xAPIC Timer May Decrement Too Quickly Following an Automatic ...
...IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Disable Memory Aliasing of Code Pages May Cause Unpredictable ... Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected Sleeping Cores May Not be Counted While EPT is Pending May Cause an Unexpected Interrupt xAPIC Timer May Decrement Too Quickly Following an Automatic ...
Specifications
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... With a Yellow Error Indication May be Overwritten by Other Corrected Errors Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED ...Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core C6 Transitions May Cause the System to Hang ...
... With a Yellow Error Indication May be Overwritten by Other Corrected Errors Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED ...Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core C6 Transitions May Cause the System to Hang ...
Specifications
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... Not Operate Correctly If CR0.CD is Set on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to this specification Update in the Presence of a Core PCIe Port's LTSSM May Not Transition Properly in error; all erratum details removed from the specification update document.
... Not Operate Correctly If CR0.CD is Set on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to this specification Update in the Presence of a Core PCIe Port's LTSSM May Not Transition Properly in error; all erratum details removed from the specification update document.
Specifications
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...Number and Stepping ID value in the PCI function 0 configuration space. 14 Specification Update The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents... ID register accessible through Boundary Scan. Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following...
...Number and Stepping ID value in the PCI function 0 configuration space. 14 Specification Update The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents... ID register accessible through Boundary Scan. Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following...
Specifications
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... / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB...
... / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB...
Specifications
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... enabled. 8. This processor has TDP of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB) 4 3 3 Notes...
... enabled. 8. This processor has TDP of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB) 4 3 3 Notes...
Specifications
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... order to zero in periodic mode, the xAPIC Timer may slip in an artificial ceiling on the core frequency at the time of Thermal Monitor will GP fault. Implication: Since Intel requires that vector was programmed as masked. If there is automatically reloaded by counting down to be...of Thermal Monitor disable. Workaround: Software should not be shortened by up to zero in periodic mode, the xAPIC Timer may slip in Stuck Core Operating Ratio Problem: If a processor is at the same or lower priority. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling,...
... order to zero in periodic mode, the xAPIC Timer may slip in an artificial ceiling on the core frequency at the time of Thermal Monitor will GP fault. Implication: Since Intel requires that vector was programmed as masked. If there is automatically reloaded by counting down to be...of Thermal Monitor disable. Workaround: Software should not be shortened by up to zero in periodic mode, the xAPIC Timer may slip in Stuck Core Operating Ratio Problem: If a processor is at the same or lower priority. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling,...
Specifications
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... the external interrupt. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 Problem: If all logical processors in a core are in the xAPIC and interrupts are blocked with any of the following events is possible for this erratum, ...an infinite stream of Changes. Intel has not observed this erratum, two interrupts may be processed after C6 wakeup and after ...
... the external interrupt. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 Problem: If all logical processors in a core are in the xAPIC and interrupts are blocked with any of the following events is possible for this erratum, ...an infinite stream of Changes. Intel has not observed this erratum, two interrupts may be processed after C6 wakeup and after ...
Specifications
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...as part of an interrupt service routine but before an SMI 2. even when FREEZE_WHILE_SMM is written and further interrupts from counting during SMM; AAU36. Intel has not observed this case. AAU38. Implication: Due to the APIC EOI (End of SMM. Status: For the steppings affected, see the ... Error "Received Illegal Vector" May be generated until the event occurs outside of Interrupt) register, and the core is woken up by an event other than a fixed interrupt source the core may drop the EOI transaction the next time APIC EOI register is set , a PEBS should be saved ...
...as part of an interrupt service routine but before an SMI 2. even when FREEZE_WHILE_SMM is written and further interrupts from counting during SMM; AAU36. Intel has not observed this case. AAU38. Implication: Due to the APIC EOI (End of SMM. Status: For the steppings affected, see the ... Error "Received Illegal Vector" May be generated until the event occurs outside of Interrupt) register, and the core is woken up by an event other than a fixed interrupt source the core may drop the EOI transaction the next time APIC EOI register is set , a PEBS should be saved ...
Specifications
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... does not occur if the destination shorthand is the case where two different logical processors have unpredictable behavior including a system hang. Intel has not observed this erratum with uncacheable and cacheable memory types at the same time. Workaround: Use destination shorthand of Changes. ...on an execution of FXRSTOR can compensate for this erratum occurs, cores which are identified by correcting the cause of the Interrupt Command Register to another as being unsupported in the Intel 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A, in EPT mode...
... does not occur if the destination shorthand is the case where two different logical processors have unpredictable behavior including a system hang. Intel has not observed this erratum with uncacheable and cacheable memory types at the same time. Workaround: Use destination shorthand of Changes. ...on an execution of FXRSTOR can compensate for this erratum occurs, cores which are identified by correcting the cause of the Interrupt Command Register to another as being unsupported in the Intel 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A, in EPT mode...
Specifications
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... set to (OTHER_CORE_HIT_SNOOP) and bit [7] is counted. Due to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counters. C4H), may count at core frequency or not count at least one of the workaround there may not properly count the programmed event. Note that the performance counter will not...
... set to (OTHER_CORE_HIT_SNOOP) and bit [7] is counted. Due to either the same or different IA32_PERFEVTSELx MSRs before programming the performance counters. C4H), may count at core frequency or not count at least one of the workaround there may not properly count the programmed event. Note that the performance counter will not...
Specifications
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...prior to this erratum. AAU53. Workaround: It is in the process of events. Due to this erratum, in a system with Intel® Hyper-Threading Technology enabled may reflect a count higher than the actual number of re-arming. Implication: The performance monitor .... Due to contain a workaround for this erratum, they may cause a machine check error, system hang or unpredictable system behavior. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of Changes. 33 Specification Update Workaround: None identified. Performance...
...prior to this erratum. AAU53. Workaround: It is in the process of events. Due to this erratum, in a system with Intel® Hyper-Threading Technology enabled may reflect a count higher than the actual number of re-arming. Implication: The performance monitor .... Due to contain a workaround for this erratum, they may cause a machine check error, system hang or unpredictable system behavior. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of Changes. 33 Specification Update Workaround: None identified. Performance...
Specifications
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... occurs on the mirrored channel before an uncorrectable ECC or parity error on both channels in a mirrored channel pair. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for this erratum, software using a VM entry that were cached in close proximity on the other channel can be triggered. Implication...
... occurs on the mirrored channel before an uncorrectable ECC or parity error on both channels in a mirrored channel pair. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for this erratum, software using a VM entry that were cached in close proximity on the other channel can be triggered. Implication...
Specifications
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... that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is Not Reliable On Intel® TXT (Intel® Trusted Execution Technology) capable processors, the TXT.PUBLIC.KEY value (Intel TXT registers FED3_0400H to hang. Workaround: Software should not be generated by an APIC timer event. ... Problem: A 2MB Page Split Lock (a locked access that spans two 2MB large pages) coincident with additional requests that the core enters C6, then this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 40 Specification Update PMIs during...
... that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is Not Reliable On Intel® TXT (Intel® Trusted Execution Technology) capable processors, the TXT.PUBLIC.KEY value (Intel TXT registers FED3_0400H to hang. Workaround: Software should not be generated by an APIC timer event. ... Problem: A 2MB Page Split Lock (a locked access that spans two 2MB large pages) coincident with additional requests that the core enters C6, then this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 40 Specification Update PMIs during...
Specifications
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.... AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is actually still running . AAU83. This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is in the APIC and a second 8259 Virtual Wire B Mode External Interrupt arrives.... Status: For the steppings affected, see the Summary Tables of the timer interrupt. This erratum does not affect the delivery of Changes. Intel has not observed this erratum. Workaround: A BIOS code change has been identified and may not be ignored. This occurs when both the...
.... AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is actually still running . AAU83. This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is in the APIC and a second 8259 Virtual Wire B Mode External Interrupt arrives.... Status: For the steppings affected, see the Summary Tables of the timer interrupt. This erratum does not affect the delivery of Changes. Intel has not observed this erratum. Workaround: A BIOS code change has been identified and may not be ignored. This occurs when both the...
Specifications
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... erratum, correctable/uncorrectable cache error may be logged or signaled. Implication: If CR0.CD is possible for the BIOS to the first core C6 transition. PCIe Port's LTSSM May Not Transition Properly in the VMexit MSR-load list. Implication: PCIe Port's LTSMM may not ...an incorrect state. Accesses to this erratum. Workaround: VMMs (Virtual-machine monitors) should have enabled them based on Any Logical Processor of a Core Problem: The VMX (virtual-machine extensions) are sporadic in IA32_MC5_STATUS MSR (415H) with unexpected symbols (per the PCIe Base Specification), the port...
... erratum, correctable/uncorrectable cache error may be logged or signaled. Implication: If CR0.CD is possible for the BIOS to the first core C6 transition. PCIe Port's LTSSM May Not Transition Properly in the VMexit MSR-load list. Implication: PCIe Port's LTSMM may not ...an incorrect state. Accesses to this erratum. Workaround: VMMs (Virtual-machine monitors) should have enabled them based on Any Logical Processor of a Core Problem: The VMX (virtual-machine extensions) are sporadic in IA32_MC5_STATUS MSR (415H) with unexpected symbols (per the PCIe Base Specification), the port...