Data Sheet
Page 6
...2-12 PECI DC Electrical Limits 30 2-13 GTL+ Bus Resistance Definitions 30 2-14 Core Frequency to FSB Multiplier Configuration 31 2-15 BSEL[2:0] Frequency Table for BCLK[1:0 32 2-16 Front Side Bus...Processor Thermal Specifications 76 5-2 Intel® Core™2 Extreme Processor QX9770 Thermal Profile 78 5-3 Intel® Core™2 Extreme Processor QX9650 Thermal Profile 79 5-4 Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile 80 5-5 Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5-6 GetTemp0() Error Codes 87 6-1 Power...
...2-12 PECI DC Electrical Limits 30 2-13 GTL+ Bus Resistance Definitions 30 2-14 Core Frequency to FSB Multiplier Configuration 31 2-15 BSEL[2:0] Frequency Table for BCLK[1:0 32 2-16 Front Side Bus...Processor Thermal Specifications 76 5-2 Intel® Core™2 Extreme Processor QX9770 Thermal Profile 78 5-3 Intel® Core™2 Extreme Processor QX9650 Thermal Profile 79 5-4 Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile 80 5-5 Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5-6 GetTemp0() Error Codes 87 6-1 Power...
Data Sheet
Page 31
... BCLK[1:0] frequency. As in previous generation processors, the processor core frequency is a multiple of the processor. The processor supports Half Ratios between 7.5 and 13.5 (see Table 2-14 for the processor supported ratios). The processor bus ratio multiplier will be set at or below the rated frequency. 2. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency 1/6 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10...
... BCLK[1:0] frequency. As in previous generation processors, the processor core frequency is a multiple of the processor. The processor supports Half Ratios between 7.5 and 13.5 (see Table 2-14 for the processor supported ratios). The processor bus ratio multiplier will be set at or below the rated frequency. 2. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency 1/6 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10...
Data Sheet
Page 82
... condition, the core-frequency-to-FSB multiple utilized by reducing the power consumption within the processor. The TCC causes the processor to service any additional hardware, software drivers, or interrupt handling routines. Under this ordering. 82 Datasheet During the frequency transition, the processor is unable to adjust its operating frequency (via the bus multiplier) and input...
... condition, the core-frequency-to-FSB multiple utilized by reducing the power consumption within the processor. The TCC causes the processor to service any additional hardware, software drivers, or interrupt handling routines. Under this ordering. 82 Datasheet During the frequency transition, the processor is unable to adjust its operating frequency (via the bus multiplier) and input...
Design Guidelines
Page 37
... clock 4.2.2.2 Thermal Monitor 2 (TM2) The second method of reducing the power consumption within the processor and limiting the processor temperature. TM2 provides an efficient means of power reduction is engaged, the processor will transition to the new core operating voltage by dropping the bus-to-core multiplier to reach the target operating voltage. When the TCC is activated...
... clock 4.2.2.2 Thermal Monitor 2 (TM2) The second method of reducing the power consumption within the processor and limiting the processor temperature. TM2 provides an efficient means of power reduction is engaged, the processor will transition to the new core operating voltage by dropping the bus-to-core multiplier to reach the target operating voltage. When the TCC is activated...