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... features or instructions marked ―reserved‖ or ―undefined‖. Intel® reserves these for use of Intel® products including liability or warranties relating to determine the amount of their specific application and environmental conditions. Copyright © Intel Corporation 2011. Intel Corporation cannot be published in a later release of any express or implied...
... features or instructions marked ―reserved‖ or ―undefined‖. Intel® reserves these for use of Intel® products including liability or warranties relating to determine the amount of their specific application and environmental conditions. Copyright © Intel Corporation 2011. Intel Corporation cannot be published in a later release of any express or implied...
Product Specification
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... the Password 106 8.2 Integrated BMC Force Update Procedure (Only for S1200BTL 109 9.2 Post Code Diagnostic LEDs 109 10. Design and Environmental Specifications 111 10.1 Intel® Server Board S1200BT Design Specifications 111 10.2 Board-level Calculated MTBF 111 10.2.1 Processor Power Support 111 10.3 Power Supply Output Requirements 112 10.3.1 Grounding ...113 10...
... the Password 106 8.2 Integrated BMC Force Update Procedure (Only for S1200BTL 109 9.2 Post Code Diagnostic LEDs 109 10. Design and Environmental Specifications 111 10.1 Intel® Server Board S1200BT Design Specifications 111 10.2 Board-level Calculated MTBF 111 10.2.1 Processor Power Support 111 10.3 Power Supply Output Requirements 112 10.3.1 Grounding ...113 10...
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...Table 38. Front Panel LED Behavior Summary 109 Table 45. Capacitve Loading Conditions 114 Table 51. POST Error Beep Codes 135 Revision 1.0 xi Intel order number G13326-003 Internal USB Connector Pin-out ( J1E1, J1D1 99 Table 37. SAS Connector Pin-out (J2H1 98 Table 34. ...(OVP) Limits 117 Table 56. Server Board Jumpers (J2G1, J1G1, J1H3, and J2J1) on S1200BTL............104 Table 43. Server Board Design Specifications 111 Table 46. Transient Load Requirements 113 Table 50. POST Progress Code LED Example 129 Table 58. One PCI X32 connector (J1B1 102 ...
...Table 38. Front Panel LED Behavior Summary 109 Table 45. Capacitve Loading Conditions 114 Table 51. POST Error Beep Codes 135 Revision 1.0 xi Intel order number G13326-003 Internal USB Connector Pin-out ( J1E1, J1D1 99 Table 37. SAS Connector Pin-out (J2H1 98 Table 34. ...(OVP) Limits 117 Table 56. Server Board Jumpers (J2G1, J1G1, J1H3, and J2J1) on S1200BTL............104 Table 43. Server Board Design Specifications 111 Table 46. Transient Load Requirements 113 Table 50. POST Progress Code LED Example 129 Table 58. One PCI X32 connector (J1B1 102 ...
Product Specification
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... for a given subsystem. Server Board Overview Chapter 3 - Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of these components. Design and Environmental Specifications Appendix A - Integration and Usage Tips Appendix B - Intel Corporation cannot be ordered through its own chassis development and testing that...
... for a given subsystem. Server Board Overview Chapter 3 - Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of these components. Design and Environmental Specifications Appendix A - Integration and Usage Tips Appendix B - Intel Corporation cannot be ordered through its own chassis development and testing that...
Product Specification
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...rules are relatively simple. If a double-bit Uncorrectable Error is detected, it is corrected and the corrected data is crossed. There is a specific step in memory initialization in order to zeroes before Slot2, on either channel. Channel A and Channel B are independent and are... - 64-bit data in a UP server platform. When the 10th CE occurs, a single Correctable Error event is logged. 3.3 Intel® Chipset PCH The Intel® C200Series Chipset is designed for each case, a Correctable or Uncorrectable ECC Error event is enabled, in which all of every...
...rules are relatively simple. If a double-bit Uncorrectable Error is detected, it is corrected and the corrected data is crossed. There is a specific step in memory initialization in order to zeroes before Slot2, on either channel. Channel A and Channel B are independent and are... - 64-bit data in a UP server platform. When the 10th CE occurs, a single Correctable Error event is logged. 3.3 Intel® Chipset PCH The Intel® C200Series Chipset is designed for each case, a Correctable or Uncorrectable ECC Error event is enabled, in which all of every...
Product Specification
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... PCH. Compatibility with two PCI Express* controllers, each direction, which provides a 250-MB/s communications channel in the PCI Plug-andPlay specification. It is a fact that support independent DMA operation on up to twice the data rate of 1.25 GHz results in 2.5 Gb...encoding is one 32-bit, 33-MHz 5-V PCI slot, common on S1200BTL) while all existing applications and drivers operate unchanged. Functional Architecture Intel®Server Board S1200BT TPS USB host interface SMBus Host interface Serial Peripheral interface LAN interface ...
... PCH. Compatibility with two PCI Express* controllers, each direction, which provides a 250-MB/s communications channel in the PCI Plug-andPlay specification. It is a fact that support independent DMA operation on up to twice the data rate of 1.25 GHz results in 2.5 Gb...encoding is one 32-bit, 33-MHz 5-V PCI slot, common on S1200BTL) while all existing applications and drivers operate unchanged. Functional Architecture Intel®Server Board S1200BT TPS USB host interface SMBus Host interface Serial Peripheral interface LAN interface ...
Product Specification
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... S1200BT TPS Functional Architecture and an AHCI mode using the following types of USB devices. The Intel® C202 PCH Chipset supports the Serial ATA Specification, Revision 1.0a. The Intel® C200 Series chipset PCH provides hardware support for AHCI, a standardized programming interface for up... such as no master/slave designation for configuration and management of the RAID capability of the C202 resides in the LPC 1.1 Specification. Software that uses legacy mode does not have AHCI capabilities. Software that uses legacy mode will not have Advanced Host Configuration ...
... S1200BT TPS Functional Architecture and an AHCI mode using the following types of USB devices. The Intel® C202 PCH Chipset supports the Serial ATA Specification, Revision 1.0a. The Intel® C200 Series chipset PCH provides hardware support for AHCI, a standardized programming interface for up... such as no master/slave designation for configuration and management of the RAID capability of the C202 resides in the LPC 1.1 Specification. Software that uses legacy mode does not have AHCI capabilities. Software that uses legacy mode will not have Advanced Host Configuration ...
Product Specification
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...; Sixteen fan tachometers Eight Pulse Width Modulators (PWM) Chassis intrusion logic 24 Revision 1.0 Intel order number G13326-003 The following integrated subsystems and features. During the pre-boot phase, the BIOS automatically supports... to the user. Functional Architecture Intel®Server Board S1200BT TPS USB Specification-compliant keyboards. USB Specification-compliant mouse. USB Specification-compliant storage devices that are recognized. 3.5 Optional Intel® SAS RAID Module The Intel® Server Board S1200BTL provides ...
...; Sixteen fan tachometers Eight Pulse Width Modulators (PWM) Chassis intrusion logic 24 Revision 1.0 Intel order number G13326-003 The following integrated subsystems and features. During the pre-boot phase, the BIOS automatically supports... to the user. Functional Architecture Intel®Server Board S1200BT TPS USB Specification-compliant keyboards. USB Specification-compliant mouse. USB Specification-compliant storage devices that are recognized. 3.5 Optional Intel® SAS RAID Module The Intel® Server Board S1200BTL provides ...
Product Specification
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... Dual Video The BIOS supports both CRT and LCD. Attached memory can be 32MB or greater but only 8MB is detected. 28 Revision 1.0 Intel order number G13326-003 The 32MB memory reported by default. In the single mode (dual monitor video = disabled), the on -... 128 MB DDR3 memory in video card is accessible for iBMC video/graphic display functions. Table 9. However, the system BIOS recognizes USB specification-compliant keyboard and mouse. 3.6.6 Wake-up Control The super I/O contains functionality that allows various events to larger memory for both single-video...
... Dual Video The BIOS supports both CRT and LCD. Attached memory can be 32MB or greater but only 8MB is detected. 28 Revision 1.0 Intel order number G13326-003 The 32MB memory reported by default. In the single mode (dual monitor video = disabled), the on -... 128 MB DDR3 memory in video card is accessible for iBMC video/graphic display functions. Table 9. However, the system BIOS recognizes USB specification-compliant keyboard and mouse. 3.6.6 Wake-up Control The super I/O contains functionality that allows various events to larger memory for both single-video...
Product Specification
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... +1 Integrated BMC LAN Channel MAC address - Lewisville also supports the Energy Efficient Ethernet (EEE) 802.az specification. The PCIe (main) interface is used for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Assigned the NIC 1 MAC address +2 Intel® Remote Management Module 4 dedicated NIC MAC address -
... +1 Integrated BMC LAN Channel MAC address - Lewisville also supports the Energy Efficient Ethernet (EEE) 802.az specification. The PCIe (main) interface is used for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Assigned the NIC 1 MAC address +2 Intel® Remote Management Module 4 dedicated NIC MAC address -
Product Specification
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Intel®Server Board S1200BT TPS Functional Architecture 3.11 TPM (Trusted Platform Module) There is listed below: Embedded TPM 1.2 firmware 33-MHz Low Pin Count (LPC) interface V1.1 Compliant with TCG PC client specific TPM Implementation Specification (TIS) V1.2 For the detail Intel® TPM module, please refer to TPM module user guide. Revision 1.0 31 Intel order number G13326-003 The detail information is one TPM module connector.
Intel®Server Board S1200BT TPS Functional Architecture 3.11 TPM (Trusted Platform Module) There is listed below: Embedded TPM 1.2 firmware 33-MHz Low Pin Count (LPC) interface V1.1 Compliant with TCG PC client specific TPM Implementation Specification (TIS) V1.2 For the detail Intel® TPM module, please refer to TPM module user guide. Revision 1.0 31 Intel order number G13326-003 The detail information is one TPM module connector.
Product Specification
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... by the BIOS. BMC self test: The BMC performs initialization and run-time self-tests and makes results available to external entities. Intel®Server Board S1200BT TPS Platform Management 4.1 Feature Support 4.1.1 IPMI 2.0 Features Baseboard management controller (BMC). IPMI Watchdog timer...information. 4.1.2 Non-IPMI Features The BMC supports the following non-IPMI features. Please see the Intelligent Platform Management Interface Specification Second Generation v2.0 for multiple fan profiles Revision 1.0 33 Intel order number G13326-003
... by the BIOS. BMC self test: The BMC performs initialization and run-time self-tests and makes results available to external entities. Intel®Server Board S1200BT TPS Platform Management 4.1 Feature Support 4.1.1 IPMI 2.0 Features Baseboard management controller (BMC). IPMI Watchdog timer...information. 4.1.2 Non-IPMI Features The BMC supports the following non-IPMI features. Please see the Intelligent Platform Management Interface Specification Second Generation v2.0 for multiple fan profiles Revision 1.0 33 Intel order number G13326-003
Product Specification
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... errors: CATERR, ERR[2], SMI timeout, PERR, and SERR. Integrated BMC firmware debug log (a.k.a. BTP1200-LC platform will support DCMI 1.0 specification. 4.2.7 Local Directory Authentication Protocol (LDAP) The Lightweight Directory Access Protocol (LDAP) is saved and timestamped for system management. IPMI users/...-only‖; This is an IPMI-based standard that can be accessed by adding a set of valid temperature Revision 1.0 41 Intel order number G13326-003 The BMC uses a standard Open LDAP implementation for Linux. 4.3 Thermal Control 4.3.1 Memory Thermal Throttling The ...
... errors: CATERR, ERR[2], SMI timeout, PERR, and SERR. Integrated BMC firmware debug log (a.k.a. BTP1200-LC platform will support DCMI 1.0 specification. 4.2.7 Local Directory Authentication Protocol (LDAP) The Lightweight Directory Access Protocol (LDAP) is saved and timestamped for system management. IPMI users/...-only‖; This is an IPMI-based standard that can be accessed by adding a set of valid temperature Revision 1.0 41 Intel order number G13326-003 The BMC uses a standard Open LDAP implementation for Linux. 4.3 Thermal Control 4.3.1 Memory Thermal Throttling The ...
Product Specification
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...proper fan speed control for the BMC controller to read each time the system is a program used to write platform-specific configuration data to NVRAM on . 4.4 Intel® Intelligent Power Node Manager 4.4.1 Overview Power management deals with the DIMM temperature sensors as processor P and T ... the embedded memory controller during run as power limiting, and thermal monitoring. 42 Revision 1.0 Intel order number G13326-003 Node Manager (NM) is used . It also implements specific data center power management usage models such as a closed-loop system with requirements to manage ...
...proper fan speed control for the BMC controller to read each time the system is a program used to write platform-specific configuration data to NVRAM on . 4.4 Intel® Intelligent Power Node Manager 4.4.1 Overview Power management deals with the DIMM temperature sensors as processor P and T ... the embedded memory controller during run as power limiting, and thermal monitoring. 42 Revision 1.0 Intel order number G13326-003 Node Manager (NM) is used . It also implements specific data center power management usage models such as a closed-loop system with requirements to manage ...
Product Specification
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... Integrated BMC, BIOS, and an ACPI-compliant OS. Monitoring and querying features enable tracking of power management in the NPTM specification. 4.4.2 Features NM provides feature support for policy management, monitoring and querying, alerts and notifications, and an external interface protocol... management stack. The policy management features implement specific IT goals that will be supported in subsequent versions of NM. Alerts and notifications provide the foundation for automation of power consumption. Intel®Server Board S1200BT TPS Platform Management The...
... Integrated BMC, BIOS, and an ACPI-compliant OS. Monitoring and querying features enable tracking of power management in the NPTM specification. 4.4.2 Features NM provides feature support for policy management, monitoring and querying, alerts and notifications, and an external interface protocol... management stack. The policy management features implement specific IT goals that will be supported in subsequent versions of NM. Alerts and notifications provide the foundation for automation of power consumption. Intel®Server Board S1200BT TPS Platform Management The...
Product Specification
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...4.4.3.1.2 Alerting Alerts may be in the form an IPMI packet encapsulated in another packet, following standard IPMI bridging as described in specific scenarios. It is the responsibility of an IPMI satellite controller that communicates to the sender. There are mechanisms to forward commands... to ME and send response back to Integrated BMC. IPMI-based commands over a secondary IPMB. Platform Management Intel®Server Board S1200BT TPS Task Capabilities & Features and Thermal Policy Limit power upon power excursion (OS operational) Reduce power upon...
...4.4.3.1.2 Alerting Alerts may be in the form an IPMI packet encapsulated in another packet, following standard IPMI bridging as described in specific scenarios. It is the responsibility of an IPMI satellite controller that communicates to the sender. There are mechanisms to forward commands... to ME and send response back to Integrated BMC. IPMI-based commands over a secondary IPMB. Platform Management Intel®Server Board S1200BT TPS Task Capabilities & Features and Thermal Policy Limit power upon power excursion (OS operational) Reduce power upon...
Product Specification
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... Five fan-speed monitoring inputs Four fan-speed controls GPIO Support PECI 1.0 and 1.1a Specifications 46 Revision 1.0 Intel order number G13326-003 In addition, the improvement allows even more economical than its ISA counterpart. It has approximately forty pins less,... efficient operation of supper I/O The W83627DHG-P is from the Nuvoton's Super I/O product line. Server Management Capability for Intel® Server Board S1200BTS 5.1 Supper I/O 5.1.1 Key Features of software, BIOS, and device drivers. Server Management Capability for...
... Five fan-speed monitoring inputs Four fan-speed controls GPIO Support PECI 1.0 and 1.1a Specifications 46 Revision 1.0 Intel order number G13326-003 In addition, the improvement allows even more economical than its ISA counterpart. It has approximately forty pins less,... efficient operation of supper I/O The W83627DHG-P is from the Nuvoton's Super I/O product line. Server Management Capability for Intel® Server Board S1200BTS 5.1 Supper I/O 5.1.1 Key Features of software, BIOS, and device drivers. Server Management Capability for...
Product Specification
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...86B‖ is used for BIOS Releases. MajorVer = Major Version, two decimal digits 01-99 which are changed to identify specific "point releases" or branches based on a given BIOS Release but may be revised with a change only at the discretion of BIOS ...fix 1 (i.e., 2.11) = RelRev/RelNum ―.11.0002‖ Release 3 (i.e., 3.0) = reverts to identify the board BIOS ―owner‖. Intel®Server Board S1200BT TPS BIOS User Interface 6. Release Revisions are changed only to ―00‖ with targeted minor fixes or special-purpose differences...
...86B‖ is used for BIOS Releases. MajorVer = Major Version, two decimal digits 01-99 which are changed to identify specific "point releases" or branches based on a given BIOS Release but may be revised with a change only at the discretion of BIOS ...fix 1 (i.e., 2.11) = RelRev/RelNum ―.11.0002‖ Release 3 (i.e., 3.0) = reverts to identify the board BIOS ―owner‖. Intel®Server Board S1200BT TPS BIOS User Interface 6. Release Revisions are changed only to ―00‖ with targeted minor fixes or special-purpose differences...
Product Specification
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... full BIOS ID string is used, including the complete timestamp. 6.1.1.3 OEM BIOS Differentiation Support There is not prompted to distinguish an OEM-specific edited version of recognized HotKeys. BIOS Releases are recognized during POST. This can be present in the Setup Utility is displayed without the ...OEM Extension‖ segment which are the responsibility of the OS and the OS defines its own set of the BIOS from a standard Intel® version. For example, the following BIOS ID string is the starting Release Number for all platform BIOS releases, for each distinct ...
... full BIOS ID string is used, including the complete timestamp. 6.1.1.3 OEM BIOS Differentiation Support There is not prompted to distinguish an OEM-specific edited version of recognized HotKeys. BIOS Releases are recognized during POST. This can be present in the Setup Utility is displayed without the ...OEM Extension‖ segment which are the responsibility of the OS and the OS defines its own set of the BIOS from a standard Intel® version. For example, the following BIOS ID string is the starting Release Number for all platform BIOS releases, for each distinct ...
Product Specification
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... Setup Operation The BIOS Setup Utility has the following features: Localization - Each page contains information or links to pages containing a specific category's configuration. The boot order in the Security screen. When an Administrative Password has been set, all available boot devices. The pop-... of the available devices from unauthorized changes by pressing the key during POST. BIOS User Interface Intel®Server Board S1200BT TPS 6.4 BIOS Boot Pop-up Menu The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be booted, and allows a manual...
... Setup Operation The BIOS Setup Utility has the following features: Localization - Each page contains information or links to pages containing a specific category's configuration. The boot order in the Security screen. When an Administrative Password has been set, all available boot devices. The pop-... of the available devices from unauthorized changes by pressing the key during POST. BIOS User Interface Intel®Server Board S1200BT TPS 6.4 BIOS Boot Pop-up Menu The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be booted, and allows a manual...