Product Specification
Page 60
... of Standards, Metrology and Inspections) mark. S. Includes Intel name and D101GGC model designation. Declaring compliance to http://support.intel.com/support/motherboards/desktop/ Taiwan BSMI (Bureau of Conformity logo mark for Intel desktop boards: E210882. Includes adjacent Intel supplier code number, N-232. Includes adjacent MIC certification number: CPU-D101GGC For information about MIC certification, go to European...
... of Standards, Metrology and Inspections) mark. S. Includes Intel name and D101GGC model designation. Declaring compliance to http://support.intel.com/support/motherboards/desktop/ Taiwan BSMI (Bureau of Conformity logo mark for Intel desktop boards: E210882. Includes adjacent Intel supplier code number, N-232. Includes adjacent MIC certification number: CPU-D101GGC For information about MIC certification, go to European...
Product Specification
Page 61
...63 3.6 BIOS Updates ...64 3.7 Boot Options ...65 3.8 Adjusting Boot Speed 66 3.9 BIOS Security Features 67 3.1 Introduction The boards use an Intel BIOS that is set to view and change the BIOS settings for the computer. The FWH contains the BIOS Setup program, POST, the PCI autoconfiguration... Main Advanced Security Power Boot Exit NOTE The maintenance menu is displayed only when the Desktop Board is poweredup, the BIOS compares the CPU version and the microcode version in configure mode. 61 The initial production BIOSs are identified as GC11010N.86A. 3 Overview of BIOS and...
...63 3.6 BIOS Updates ...64 3.7 Boot Options ...65 3.8 Adjusting Boot Speed 66 3.9 BIOS Security Features 67 3.1 Introduction The boards use an Intel BIOS that is set to view and change the BIOS settings for the computer. The FWH contains the BIOS Setup program, POST, the PCI autoconfiguration... Main Advanced Security Power Boot Exit NOTE The maintenance menu is displayed only when the Desktop Board is poweredup, the BIOS compares the CPU version and the microcode version in configure mode. 61 The initial production BIOSs are identified as GC11010N.86A. 3 Overview of BIOS and...
Product Specification
Page 71
... 71 Initial Early_Init_Onboard_Generator switch. Initial interrupts vector table. Put information on screen display, including Award title, CPU type, and CPU speed. Initialize L2 cache and program CPU with proper cacheable range. 3. Initialize the APIC. 4. Prepare BIOS resource map for RTC minute. 2. Example: onboard IDE controller. 4. ...Code 14h 16h 18h 1Bh 1Dh 1Fh 21h 23h 27h 29h 2Dh 33h 3Ch 3Eh 40h 43h 47h 49h 4Eh Description of each CPU are directed to SPURIOUS_INT_HDLR and software interrupts to smaller one in case the cacheable ranges between each 64K page. 1. If no ...
... 71 Initial Early_Init_Onboard_Generator switch. Initial interrupts vector table. Put information on screen display, including Award title, CPU type, and CPU speed. Initialize L2 cache and program CPU with proper cacheable range. 3. Initialize the APIC. 4. Prepare BIOS resource map for RTC minute. 2. Example: onboard IDE controller. 4. ...Code 14h 16h 18h 1Bh 1Dh 1Fh 21h 23h 27h 29h 2Dh 33h 3Ch 3Eh 40h 43h 47h 49h 4Eh Description of each CPU are directed to SPURIOUS_INT_HDLR and software interrupts to smaller one in case the cacheable ranges between each 64K page. 1. If no ...