Programming Manual
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... are trademarks or registered trademarks of reserved or undefined features or instructions may make changes to obtain the latest specifications and before placing your hardware and software configurations. Processors will vary depending on an Intel processor. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Performance will vary depending...
... are trademarks or registered trademarks of reserved or undefined features or instructions may make changes to obtain the latest specifications and before placing your hardware and software configurations. Processors will vary depending on an Intel processor. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Performance will vary depending...
Programming Manual
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...the typical count of an event from the perspective of that track ring activity at the C-Box/Core ring stops. Processor Snoop Response Queue on AD Ring. Intel QPI ordering buffer that occur as a result of back pressure on those events). C-Box performance ...specific events that are not tracked by the C-Box PMUs are those events are tracking ring activity at the C-Box/Core sink inject points. Associated with requests from C to S-Box. There are events in the C-Box for each C-Box instance. Ingress GO-pending (tracking GO's to Core. INTEL® XEON® PROCESSOR...
...the typical count of an event from the perspective of that track ring activity at the C-Box/Core ring stops. Processor Snoop Response Queue on AD Ring. Intel QPI ordering buffer that occur as a result of back pressure on those events). C-Box performance ...specific events that are not tracked by the C-Box PMUs are those events are tracking ring activity at the C-Box/Core sink inject points. Associated with requests from C to S-Box. There are events in the C-Box for each C-Box instance. Ingress GO-pending (tracking GO's to Core. INTEL® XEON® PROCESSOR...
Programming Manual
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... are counting from reset de-assertion. 2.3.4.4 Detecting Performance Problems in -between the Core and the Ring buffering messages as those messages transit between transactions and loads are not localized to specific C-Boxes. 2.3.5 C-Box Events Ordered By Code Table 2-15 summarizes the directly-...IPQ then the C-Box hasn't acknowledged it yet and the request hasn't yet entered the LLC's "coherence domain". INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.4.3 The Queues: There are manifesting when the C-Box starts to get ...
... are counting from reset de-assertion. 2.3.4.4 Detecting Performance Problems in -between the Core and the Ring buffering messages as those messages transit between transactions and loads are not localized to specific C-Boxes. 2.3.5 C-Box Events Ordered By Code Table 2-15 summarizes the directly-...IPQ then the C-Box hasn't acknowledged it yet and the request hasn't yet entered the LLC's "coherence domain". INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.4.3 The Queues: There are manifesting when the C-Box starts to get ...
Programming Manual
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... to the coupled M-Box must be also configured (by a maximum of 1 per cycle. All requests for memory attached to selected cores when it receives this conflict checking. Each of these four counters is dedicated to monitor events) and the overflow bit(s) has been...about how to respond to see a new freeze, the overflow field responsible for the freeze, found in the Intel® QuickPath Interconnect Specification). INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.4 B-Box Performance Monitoring 2.4.1 Overview of the B-Box The B-...
... to the coupled M-Box must be also configured (by a maximum of 1 per cycle. All requests for memory attached to selected cores when it receives this conflict checking. Each of these four counters is dedicated to monitor events) and the overflow bit(s) has been...about how to respond to see a new freeze, the overflow field responsible for the freeze, found in the Intel® QuickPath Interconnect Specification). INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.4 B-Box Performance Monitoring 2.4.1 Overview of the B-Box The B-...
Programming Manual
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...B_MSR_PMON_GLOBAL_CTL Register - Counter/Control Pairs + Filters The following table defines the layout of these configuration registers is detected from a specific set . Setting the .ev_sel field performs the event selection. Field Definitions Field ctr_en Bits HW Reset Val Description 3:0 ...by setting the corresponding bit in B_MSR_PMON_GLOBAL_OVF_CTL Table 2-19. NOTE: This bit is detected. Table 2-18. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-17. Field Definitions Field clr_ov Bits HW Reset Val...
...B_MSR_PMON_GLOBAL_CTL Register - Counter/Control Pairs + Filters The following table defines the layout of these configuration registers is detected from a specific set . Setting the .ev_sel field performs the event selection. Field Definitions Field ctr_en Bits HW Reset Val Description 3:0 ...by setting the corresponding bit in B_MSR_PMON_GLOBAL_OVF_CTL Table 2-19. NOTE: This bit is detected. Table 2-18. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-17. Field Definitions Field clr_ov Bits HW Reset Val...
Programming Manual
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...0x0A, Max. all IOH triggered memory transactions targeting this B-Box as their home node and processed by incoming transaction. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_FULL • Title: IMT Full • Category: In-Flight ...100) is > ~5%, it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. 2-38 Inc/Cyc: 1, PERF_CTL: 1, • Definition: Inserts (all InvItoE memory transactions targeting this B-Box) ...
...0x0A, Max. all IOH triggered memory transactions targeting this B-Box as their home node and processed by incoming transaction. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_FULL • Title: IMT Full • Category: In-Flight ...100) is > ~5%, it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. 2-38 Inc/Cyc: 1, PERF_CTL: 1, • Definition: Inserts (all InvItoE memory transactions targeting this B-Box) ...
Programming Manual
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... derive average IMT latency or latency for specific flavors of inserts. IMT_INSERTS_NON_IOH_WR • Title: IMT Non-IOH Write Inserts • Category: In-Flight Memory Table • Event Code: 0x0E, Max. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE ... 100) is > ~5%, it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. 2-39 Inc/Cyc: 1, PERF_CTL: 1, • Definition: In-Flight Memory Table Write IOH Request Inserts (e.g. If the ...
... derive average IMT latency or latency for specific flavors of inserts. IMT_INSERTS_NON_IOH_WR • Title: IMT Non-IOH Write Inserts • Category: In-Flight Memory Table • Event Code: 0x0E, Max. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE ... 100) is > ~5%, it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. 2-39 Inc/Cyc: 1, PERF_CTL: 1, • Definition: In-Flight Memory Table Write IOH Request Inserts (e.g. If the ...
Programming Manual
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... 2, • Definition: Number of SB Link (B to S) Messages (multiply by 32 to derive average IMT latency or latency for specific flavors of valid entries is not recommended that this B-Box) • NOTE: Conflicts and AckConflicts are considered IMT insert events. IMT_INSERTS_WR ... with IMT_VALID_OCCUPANCY) be used to this B-Box) • NOTE: Conflicts and AckConflicts are considered IMT insert events. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_RD • Title: IMT Read Inserts • Category: In-Flight...
... 2, • Definition: Number of SB Link (B to S) Messages (multiply by 32 to derive average IMT latency or latency for specific flavors of valid entries is not recommended that this B-Box) • NOTE: Conflicts and AckConflicts are considered IMT insert events. IMT_INSERTS_WR ... with IMT_VALID_OCCUPANCY) be used to this B-Box) • NOTE: Conflicts and AckConflicts are considered IMT insert events. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_RD • Title: IMT Read Inserts • Category: In-Flight...
Programming Manual
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...to various standard packet fields such as message class, opcode, etc. (NOTE: specifically goes with the C-Box(es) as the Intel QPI caching agent(s). Once the global controls have been locally enabled (.en bit ...INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.5 S-Box Performance Monitoring 2.5.1 Overview of the S-Box The S-Box represents the interface between the C and R & B-Boxes. It manages flow control between the last level cache and the system interface. The S-Box is prepared for converting C-box requests to selected cores...
...to various standard packet fields such as message class, opcode, etc. (NOTE: specifically goes with the C-Box(es) as the Intel QPI caching agent(s). Once the global controls have been locally enabled (.en bit ...INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.5 S-Box Performance Monitoring 2.5.1 Overview of the S-Box The S-Box represents the interface between the C and R & B-Boxes. It manages flow control between the last level cache and the system interface. The S-Box is prepared for converting C-box requests to selected cores...
Programming Manual
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...specifies the port resources. R-Box PMUs are split. R-Box PMUs do not provide any event per port. QPI0) 2-73 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual wire that...the crossbar from input to output port) by the R-Box according to various standard packet fields such as defined by the Intel® QuickPath Interconnect Specification. Each control register can monitor events occurring on how to setup a monitoring session, refer to Section 2.1.2, "Setting up...
...specifies the port resources. R-Box PMUs are split. R-Box PMUs do not provide any event per port. QPI0) 2-73 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual wire that...the crossbar from input to output port) by the R-Box according to various standard packet fields such as defined by the Intel® QuickPath Interconnect Specification. Each control register can monitor events occurring on how to setup a monitoring session, refer to Section 2.1.2, "Setting up...
Programming Manual
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... controller is the interface between the home node controller (B-Box) and the Intel Scalable Memory Interconnect and basically translates read and write commands into specific Intel® Scalable Memory Interconnect (Intel® SMI) operations. The memory controller also provides a variety of the... There are two memory controllers per socket, each B-Box is , B-Boxes and memory controllers come in lockstep. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7 M-Box Performance Monitoring 2.7.1 Overview of the M-Box The memory ...
... controller is the interface between the home node controller (B-Box) and the Intel Scalable Memory Interconnect and basically translates read and write commands into specific Intel® Scalable Memory Interconnect (Intel® SMI) operations. The memory controller also provides a variety of the... There are two memory controllers per socket, each B-Box is , B-Boxes and memory controllers come in lockstep. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7 M-Box Performance Monitoring 2.7.1 Overview of the M-Box The memory ...