Programming Manual
Page 2
...the specific hardware and software you use . including details on hardware and software configurations. Intel® Virtualization Technology requires a computer system with an Intel® processor supporting Hyper-Threading Technology and an HT Technology enabled chipset, BIOS and operating system. ....htm; Hyper-Threading Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for Intel® 64 architecture. Copies of reserved or undefined features or instructions...
...the specific hardware and software you use . including details on hardware and software configurations. Intel® Virtualization Technology requires a computer system with an Intel® processor supporting Hyper-Threading Technology and an HT Technology enabled chipset, BIOS and operating system. ....htm; Hyper-Threading Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for Intel® 64 architecture. Copies of reserved or undefined features or instructions...
Programming Manual
Page 85
... PMUs. At a high level, the R-Box PMU supports features comparable to other peripheral control registers. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual wire that allow a user to match packets serviced (packet is possible to monitor up to...
... PMUs. At a high level, the R-Box PMU supports features comparable to other peripheral control registers. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual wire that allow a user to match packets serviced (packet is possible to monitor up to...
Programming Manual
Page 98
...certain DRS messages) 0x0 Reserved; R_MSR_PORT{7-0}_XBR_SET{2-1}_MATCH Registers (Sheet 2 of opcodes that may be filtered per message class. 4:3 0x0 Virtual Network b00 - Following is undefined. 0x0 Destination Node ID 0x0 Message Class 0x0 Opcode VNW --- Must write to 0 else behavior is... 0x0 Response Data State (for a listing of 2) Bits HW Reset Val 12:9 0x0 Message Class Description b0000 HOM - INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field MC OPC VNW --- Table 2-51. VN1 b1x - Must write to ...
...certain DRS messages) 0x0 Reserved; R_MSR_PORT{7-0}_XBR_SET{2-1}_MATCH Registers (Sheet 2 of opcodes that may be filtered per message class. 4:3 0x0 Virtual Network b00 - Following is undefined. 0x0 Destination Node ID 0x0 Message Class 0x0 Opcode VNW --- Must write to 0 else behavior is... 0x0 Response Data State (for a listing of 2) Bits HW Reset Val 12:9 0x0 Message Class Description b0000 HOM - INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field MC OPC VNW --- Table 2-51. VN1 b1x - Must write to ...
Programming Manual
Page 104
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING NEW_PACKETS_RECV • Title: New Packets Received by Port • Category: RIX • [Bit(s)] Value: see table, Max. ... • Title: Null Idle Flits • Category: RIX • [Bit(s)] Value: [30]0x1, Max. Inc/Cyc: 1, • Definition: Counts new packets received according to the Virtual Network and Message Class speci- Extension VN0.NCB VN0.NCS VN0.DRS VN0.NDR VN0.SNP VN0.HOM VN0.ALL VN1.NCB VN1.NCS VN1...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING NEW_PACKETS_RECV • Title: New Packets Received by Port • Category: RIX • [Bit(s)] Value: see table, Max. ... • Title: Null Idle Flits • Category: RIX • [Bit(s)] Value: [30]0x1, Max. Inc/Cyc: 1, • Definition: Counts new packets received according to the Virtual Network and Message Class speci- Extension VN0.NCB VN0.NCS VN0.DRS VN0.NDR VN0.SNP VN0.HOM VN0.ALL VN1.NCB VN1.NCS VN1...