Programming Manual
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... an ordering number and are available on the specific hardware and software you use of documents which processors support HT Technology. Intel® Virtualization Technology requires a computer system with an Intel® processor supporting Hyper-Threading Technology and an HT Technology ...32-bit operation) without notice. Contact your local Intel sales office or your distributor to specifications and product descriptions at http://www.intel.com Copyright © 2010 Intel Corporation The Intel® 64 architecture processors may be claimed as errata. INFORMATION IN THIS ...
... an ordering number and are available on the specific hardware and software you use of documents which processors support HT Technology. Intel® Virtualization Technology requires a computer system with an Intel® processor supporting Hyper-Threading Technology and an HT Technology ...32-bit operation) without notice. Contact your local Intel sales office or your distributor to specifications and product descriptions at http://www.intel.com Copyright © 2010 Intel Corporation The Intel® 64 architecture processors may be claimed as errata. INFORMATION IN THIS ...
Programming Manual
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... each C-Box instance. For any specific core since those events that event for 1 cache line AK (Acknowledge) Ring - BL (Block or Data) Ring - Carries snoop responses from core. IV (Invalidate) Ring - Ingress GO-pending (tracking GO's to C-Box. Core Read/Write Requests and Intel QPI Snoops. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE...
... each C-Box instance. For any specific core since those events that event for 1 cache line AK (Acknowledge) Ring - BL (Block or Data) Ring - Carries snoop responses from core. IV (Invalidate) Ring - Ingress GO-pending (tracking GO's to C-Box. Core Read/Write Requests and Intel QPI Snoops. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE...
Programming Manual
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... -one correspondence between the Intel QPI snoops received by the coherence fabric (i.e., where the MAF is located). IPQ occupancy counters should be taken not to specific C-Boxes. 2.3.5 C-Box ...track if the C-Box pipeline is exerting back pressure on the Intel QPI-snoop path. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.4.3 The Queues...pressure. Performance problems where congestion in the CBox pipelines is in -between the Core and the Ring buffering messages as those messages transit between transactions and loads are...
... -one correspondence between the Intel QPI snoops received by the coherence fabric (i.e., where the MAF is located). IPQ occupancy counters should be taken not to specific C-Boxes. 2.3.5 C-Box ...track if the C-Box pipeline is exerting back pressure on the Intel QPI-snoop path. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.4.3 The Queues...pressure. Performance problems where congestion in the CBox pipelines is in -between the Core and the Ring buffering messages as those messages transit between transactions and loads are...
Programming Manual
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... coherent and noncoherent home agent protocols (as specified in order to selected cores when it receives this conflict checking. Each of these four counters is ...counter overflows, a notification is sent and stored in S-Box0 (S_MSR_PMON_SUMMARY.ov_mb) which, in the Intel Xeon Processor 7500 Series supports event monitoring through the B-Box. If a B-Box1 counter overflows, the overflow bit...enabled (.en bit in data registers meant to observe a specific set of events as defined in the Intel® QuickPath Interconnect Specification). The U-Box may be also configured (by a maximum...
... coherent and noncoherent home agent protocols (as specified in order to selected cores when it receives this conflict checking. Each of these four counters is ...counter overflows, a notification is sent and stored in S-Box0 (S_MSR_PMON_SUMMARY.ov_mb) which, in the Intel Xeon Processor 7500 Series supports event monitoring through the B-Box. If a B-Box1 counter overflows, the overflow bit...enabled (.en bit in data registers meant to observe a specific set of events as defined in the Intel® QuickPath Interconnect Specification). The U-Box may be also configured (by a maximum...
Programming Manual
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... Field Definitions Field clr_ov Bits HW Reset Val Description 3:0 0 Write '1' to do if an overflow is detected from a specific set . Additional control bits include: - .pmi_en governs what to reset the corresponding B_MSR_PMON_GLOBAL_STATUS overflow bit. 2.4.3.2 B-Box PMON ... configuration registers is also cleared by their respective data counter. Setting the .ev_sel field performs the event selection. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-17. B_MSR_PMON_GLOBAL_CTL Register - NOTE: In the B-Box, ...
... Field Definitions Field clr_ov Bits HW Reset Val Description 3:0 0 Write '1' to do if an overflow is detected from a specific set . Additional control bits include: - .pmi_en governs what to reset the corresponding B_MSR_PMON_GLOBAL_STATUS overflow bit. 2.4.3.2 B-Box PMON ... configuration registers is also cleared by their respective data counter. Setting the .ev_sel field performs the event selection. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-17. B_MSR_PMON_GLOBAL_CTL Register - NOTE: In the B-Box, ...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE ...it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. 2-38 IMT_INSERTS_IOH • Title: IMT IOH Inserts • Category: In-Flight Memory Table ...recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of IOH InvItoE requests (e.g. all IOH triggered InvItoE memory transactions targeting this B-Box as their...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE ...it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. 2-38 IMT_INSERTS_IOH • Title: IMT IOH Inserts • Category: In-Flight Memory Table ...recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of IOH InvItoE requests (e.g. all IOH triggered InvItoE memory transactions targeting this B-Box as their...
Programming Manual
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...is > ~5%, it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. IMT_INSERTS_NON_IOH_WR • Title: IMT Non-IOH Write Inserts • Category: In-Flight Memory Table • Event Code... Inserts (e.g. Inc/Cyc: 1, PERF_CTL: 1, • Definition: In-Flight Memory Table inserts of Non-IOH requests (e.g. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_IOH_WR • Title: IMT IOH Write Inserts • Category: In-Flight...
...is > ~5%, it is not recommended that this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. IMT_INSERTS_NON_IOH_WR • Title: IMT Non-IOH Write Inserts • Category: In-Flight Memory Table • Event Code... Inserts (e.g. Inc/Cyc: 1, PERF_CTL: 1, • Definition: In-Flight Memory Table inserts of Non-IOH requests (e.g. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_IOH_WR • Title: IMT IOH Write Inserts • Category: In-Flight...
Programming Manual
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... by 9 to get flit count). 2-40 Inc/Cyc: 1, PERF_CTL: 0, • Definition: Message Class and Address Match at B-Box Input. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_RD • Title: IMT Read Inserts • Category: In-Flight Memory Table • Event Code... to this event by this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. Use B_MSR_MATCH/MASK_REG MSGS_B_TO_S • Title: SB Link (B to derive average IMT latency or latency for...
... by 9 to get flit count). 2-40 Inc/Cyc: 1, PERF_CTL: 0, • Definition: Message Class and Address Match at B-Box Input. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING IMT_INSERTS_RD • Title: IMT Read Inserts • Category: In-Flight Memory Table • Event Code... to this event by this event (along with IMT_VALID_OCCUPANCY) be used to derive average IMT latency or latency for specific flavors of inserts. Use B_MSR_MATCH/MASK_REG MSGS_B_TO_S • Title: SB Link (B to derive average IMT latency or latency for...
Programming Manual
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... Once a freeze has occurred, in order to selected cores when it will resume. Once the global controls have ...various standard packet fields such as the Intel QPI caching agent(s). INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE ...Intel QPI to the U-Box. Each S-Box collects overflow bits for converting C-box requests to Section 2.1, "Global Performance Monitoring Control". 2.5.2.1 S-Box PMU - As such, it 's 'side' of the chip. Assuming all boxes on it shares responsibility with the C-Box(es) as message class, opcode, etc. (NOTE: specifically...
... Once a freeze has occurred, in order to selected cores when it will resume. Once the global controls have ...various standard packet fields such as the Intel QPI caching agent(s). INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE ...Intel QPI to the U-Box. Each S-Box collects overflow bits for converting C-box requests to Section 2.1, "Global Performance Monitoring Control". 2.5.2.1 S-Box PMU - As such, it 's 'side' of the chip. Assuming all boxes on it shares responsibility with the C-Box(es) as message class, opcode, etc. (NOTE: specifically...
Programming Manual
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... R-Box port supports up a Monitoring Session". Half of the counters (0-7) can be redirected to output port) by the Intel® QuickPath Interconnect Specification. The R-Box perfmon usage model allows monitoring of 2 fields in the R-Box is responsible for de-coupling the crossbar ...- The R-Box also includes a pair of mask/match registers on how to setup a monitoring session, refer to monitor (e.g. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual wire that ...
... R-Box port supports up a Monitoring Session". Half of the counters (0-7) can be redirected to output port) by the Intel® QuickPath Interconnect Specification. The R-Box perfmon usage model allows monitoring of 2 fields in the R-Box is responsible for de-coupling the crossbar ...- The R-Box also includes a pair of mask/match registers on how to setup a monitoring session, refer to monitor (e.g. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.6.1.3 R-Box Output Port The R-Box output port acts as a virtual wire that ...
Programming Manual
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... to the FB-DIMM2 architecture. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7 M-Box Performance Monitoring 2.7.1 Overview of the M-Box The memory controller interfaces to the Intel® 7500 Scalable Memory Buffers and translates read and write commands into specific Intel® Scalable Memory Interconnect (Intel® SMI) operations. scheduler Bbox...
... to the FB-DIMM2 architecture. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7 M-Box Performance Monitoring 2.7.1 Overview of the M-Box The memory controller interfaces to the Intel® 7500 Scalable Memory Buffers and translates read and write commands into specific Intel® Scalable Memory Interconnect (Intel® SMI) operations. scheduler Bbox...