Programming Manual
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... BIOS and VMM applications are trademarks or registered trademarks of Intel Corporation or its subsidiaries in development. 64-bit computing on which have no responsibility whatsoever for Intel® 64 architecture. Developers must not rely on an Intel processor. Improper use of any time, without an Intel® 64 architecture-enabled BIOS. Current characterized errata are referenced in developer...
... BIOS and VMM applications are trademarks or registered trademarks of Intel Corporation or its subsidiaries in development. 64-bit computing on which have no responsibility whatsoever for Intel® 64 architecture. Developers must not rely on an Intel processor. Improper use of any time, without an Intel® 64 architecture-enabled BIOS. Current characterized errata are referenced in developer...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.2 U-Box Performance Monitoring The U-Box serves as the system configuration controller for more information. 2.2.1.2 U-Box PMON state - The .en bit must also be enabled in the uncore global state registers. Table...data counter. U-Box Performance Monitoring MSRs MSR Name U_MSR_PMON_CTR U_MSR_PMON_EV_SEL Access MSR Address Size (bits) Description RW_RW 0x0C11 64 U-Box PMON Counter RW_RO 0x0C10 32 U-Box PMON Event Select 2.2.1.1 U-Box Box Level PMON State U-Box global...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.2 U-Box Performance Monitoring The U-Box serves as the system configuration controller for more information. 2.2.1.2 U-Box PMON state - The .en bit must also be enabled in the uncore global state registers. Table...data counter. U-Box Performance Monitoring MSRs MSR Name U_MSR_PMON_CTR U_MSR_PMON_EV_SEL Access MSR Address Size (bits) Description RW_RW 0x0C11 64 U-Box PMON Counter RW_RO 0x0C10 32 U-Box PMON Event Select 2.2.1.1 U-Box Box Level PMON State U-Box global...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.3 C-BOX Performance Monitors Table 2-9. C-Box Performance Monitoring MSRs MSR Name Acces s MSR Addres s Size (bits ) Description CB7_CR_C_MSR_PMON_CTR_5 RW_R W 0xDFB 64 C-Box 7 PMON Counter 5 CB7_CR_C_MSR_PMON_EVT_SEL_5 RW_RO 0xDFA 64 C-Box 7 PMON Event Select 5 CB7_CR_C_MSR_PMON_CTR_4 RW_R W 0xDF9 64 C-Box 7 PMON Counter 4 CB7_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xDF8 64 C-Box 7 PMON Event...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.3.3 C-BOX Performance Monitors Table 2-9. C-Box Performance Monitoring MSRs MSR Name Acces s MSR Addres s Size (bits ) Description CB7_CR_C_MSR_PMON_CTR_5 RW_R W 0xDFB 64 C-Box 7 PMON Counter 5 CB7_CR_C_MSR_PMON_EVT_SEL_5 RW_RO 0xDFA 64 C-Box 7 PMON Event Select 5 CB7_CR_C_MSR_PMON_CTR_4 RW_R W 0xDF9 64 C-Box 7 PMON Counter 4 CB7_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xDF8 64 C-Box 7 PMON Event...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB5_CR_C_MSR_PMON_CTR_5 RW_R W 0xDBB 64 C-Box 5 PMON Counter 5 CB5_CR_C_MSR_PMON_EVT_SEL_5 RW_RO 0xDBA 64 C-Box 5 PMON Event Select 5 CB5_CR_C_MSR_PMON_CTR_4 RW_R W 0xDB9 64 C-Box 5 PMON Counter 4 CB5_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xDB8 64 C-Box 5 PMON Event Select 4 CB5_CR_C_MSR_PMON_CTR_3 RW_R W 0xDB7 64 C-Box 5 PMON Counter 3 CB5_CR_C_MSR_PMON_EVT_SEL_3...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB5_CR_C_MSR_PMON_CTR_5 RW_R W 0xDBB 64 C-Box 5 PMON Counter 5 CB5_CR_C_MSR_PMON_EVT_SEL_5 RW_RO 0xDBA 64 C-Box 5 PMON Event Select 5 CB5_CR_C_MSR_PMON_CTR_4 RW_R W 0xDB9 64 C-Box 5 PMON Counter 4 CB5_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xDB8 64 C-Box 5 PMON Event Select 4 CB5_CR_C_MSR_PMON_CTR_3 RW_R W 0xDB7 64 C-Box 5 PMON Counter 3 CB5_CR_C_MSR_PMON_EVT_SEL_3...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB6_CR_C_MSR_PMON_CTR_4 RW_R W 0xD79 64 C-Box 6 PMON Counter 4 CB6_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xD78 64 C-Box 6 PMON Event Select 4 CB6_CR_C_MSR_PMON_CTR_3 RW_R W 0xD77 64 C-Box 6 PMON Counter 3 CB6_CR_C_MSR_PMON_EVT_SEL_3 RW_RO 0xD76 64 C-Box 6 PMON Event Select 3 CB6_CR_C_MSR_PMON_CTR_2 RW_R W 0xD75 64 C-Box 6 PMON Counter 2 CB6_CR_C_MSR_PMON_EVT_SEL_2...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB6_CR_C_MSR_PMON_CTR_4 RW_R W 0xD79 64 C-Box 6 PMON Counter 4 CB6_CR_C_MSR_PMON_EVT_SEL_4 RW_RO 0xD78 64 C-Box 6 PMON Event Select 4 CB6_CR_C_MSR_PMON_CTR_3 RW_R W 0xD77 64 C-Box 6 PMON Counter 3 CB6_CR_C_MSR_PMON_EVT_SEL_3 RW_RO 0xD76 64 C-Box 6 PMON Event Select 3 CB6_CR_C_MSR_PMON_CTR_2 RW_R W 0xD75 64 C-Box 6 PMON Counter 2 CB6_CR_C_MSR_PMON_EVT_SEL_2...
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... register can collect events. 2-13 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB4_CR_C_MSR_PMON_CTR_3 RW_R W 0xD37 64 C-Box 4 PMON Counter 3 CB4_CR_C_MSR_PMON_EVT_SEL_3 RW_RO 0xD36 64 C-Box 4 PMON Event Select 3 CB4_CR_C_MSR_PMON_CTR_2 RW_R W 0xD35 64 C-Box 4 PMON Counter 2 CB4_CR_C_MSR_PMON_EVT_SEL_2 RW_RO 0xD34 64 C-Box 4 PMON Event Select 2 CB4_CR_C_MSR_PMON_CTR_1...
... register can collect events. 2-13 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Acces s MSR Addres s Size (bits ) Description CB4_CR_C_MSR_PMON_CTR_3 RW_R W 0xD37 64 C-Box 4 PMON Counter 3 CB4_CR_C_MSR_PMON_EVT_SEL_3 RW_RO 0xD36 64 C-Box 4 PMON Event Select 3 CB4_CR_C_MSR_PMON_CTR_2 RW_R W 0xD35 64 C-Box 4 PMON Counter 2 CB4_CR_C_MSR_PMON_EVT_SEL_2 RW_RO 0xD34 64 C-Box 4 PMON Event Select 2 CB4_CR_C_MSR_PMON_CTR_1...
Programming Manual
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...Address Size (bits) Description RW_RW 0x0E4E 64 B-Box 1 PMON Mask Register RW_RW 0x0E4D 64 B-Box 1 PMON Match Register RW_RW 0x0E46 64 B-Box 0 PMON Mask Register RW_RW 0x0E45 64 B-Box 0 PMON Match Register BB1_CR_B_MSR_PERF_CNT3_REG RW_RW 0x0C77 64 B-Box 1 PMON Counter 3 BB1_CR_B_MSR_PERF_CTL3_REG RW_RW 0x0C76 64 B-Box ...PMON registers, the corresponding bit in the _GLOBAL_STATUS.ov field will be set the corresponding bits in the B-Box. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a user must set . INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING ...
...Address Size (bits) Description RW_RW 0x0E4E 64 B-Box 1 PMON Mask Register RW_RW 0x0E4D 64 B-Box 1 PMON Match Register RW_RW 0x0E46 64 B-Box 0 PMON Mask Register RW_RW 0x0E45 64 B-Box 0 PMON Match Register BB1_CR_B_MSR_PERF_CNT3_REG RW_RW 0x0C77 64 B-Box 1 PMON Counter 3 BB1_CR_B_MSR_PERF_CTL3_REG RW_RW 0x0C76 64 B-Box ...PMON registers, the corresponding bit in the _GLOBAL_STATUS.ov field will be set the corresponding bits in the B-Box. To reset the overflow bits set in the _GLOBAL_STATUS.ov field, a user must set . INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING ...
Programming Manual
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...opcode, etc. (NOTE: specifically goes with the C-Box(es) as converting/forwarding ring messages to selected cores when it 's 'side' of the chip. It manages flow control between the last level cache and the system interface. Each...MSR Name SS1_CR_S_MSR_MASK SS1_CR_S_MSR_MATCH SS1_CR_S_MSR_MM_CFG Access MSR Address Size (bits) Description RW_RO 0x0E5A 64 S-Box 1 Enable Mask Register RW_RO 0x0E59 64 S-Box 1 Enable Match Register RW_NA 0x0E58 64 S-Box 1 Enable Match/Mask Config 2-45 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.5 ...
...opcode, etc. (NOTE: specifically goes with the C-Box(es) as converting/forwarding ring messages to selected cores when it 's 'side' of the chip. It manages flow control between the last level cache and the system interface. Each...MSR Name SS1_CR_S_MSR_MASK SS1_CR_S_MSR_MATCH SS1_CR_S_MSR_MM_CFG Access MSR Address Size (bits) Description RW_RO 0x0E5A 64 S-Box 1 Enable Mask Register RW_RO 0x0E59 64 S-Box 1 Enable Match Register RW_NA 0x0E58 64 S-Box 1 Enable Match/Mask Config 2-45 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.5 ...
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Access MSR Address Size (bits) Description SS0_CR_S_MSR_MASK SS0_CR_S_MSR_MATCH SS0_CR_S_MSR_MM_CFG RW_RO 0x0E4A 64 S-Box 0 Enable Mask Register RW_RO 0x0E49 64 S-Box 0 Enable Match Register RW_NA 0x0E48 64 S-Box 0 Enable Match/Mask Config SR1_CR_S_MSR_PMON_CTR3 SR1_CR_S_MSR_PMON_CTL3 SR1_CR_S_MSR_PMON_CTR2 SR1_CR_S_MSR_PMON_CTL2 SR1_CR_S_MSR_PMON_CTR1 SR1_CR_S_MSR_PMON_CTL1 SR1_CR_S_MSR_PMON_CTR0 SR1_CR_S_MSR_PMON_CTL0 RW_RW 0x0CD7 64 S-Box...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name Access MSR Address Size (bits) Description SS0_CR_S_MSR_MASK SS0_CR_S_MSR_MATCH SS0_CR_S_MSR_MM_CFG RW_RO 0x0E4A 64 S-Box 0 Enable Mask Register RW_RO 0x0E49 64 S-Box 0 Enable Match Register RW_NA 0x0E48 64 S-Box 0 Enable Match/Mask Config SR1_CR_S_MSR_PMON_CTR3 SR1_CR_S_MSR_PMON_CTL3 SR1_CR_S_MSR_PMON_CTR2 SR1_CR_S_MSR_PMON_CTL2 SR1_CR_S_MSR_PMON_CTR1 SR1_CR_S_MSR_PMON_CTL1 SR1_CR_S_MSR_PMON_CTR0 SR1_CR_S_MSR_PMON_CTL0 RW_RW 0x0CD7 64 S-Box...
Programming Manual
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... counter is a 7b queue occupancy counter which can be used to the performance counter each of the four general purpose counters is 64 (for buffering traffic into one entry per cycle b) The entire 7b from the 'selected' (by the event select) queue occ...as bypass use (i.e. NO_CREDIT_SNP). it must match the corresponding address match bit in Section 2.5.5, "S-Box Events Ordered By Code". EGRESS_BYPASS) and when output credit is NOT matched 0 - INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ig addr hnid Table...
... counter is a 7b queue occupancy counter which can be used to the performance counter each of the four general purpose counters is 64 (for buffering traffic into one entry per cycle b) The entire 7b from the 'selected' (by the event select) queue occ...as bypass use (i.e. NO_CREDIT_SNP). it must match the corresponding address match bit in Section 2.5.5, "S-Box Events Ordered By Code". EGRESS_BYPASS) and when output credit is NOT matched 0 - INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Field ig addr hnid Table...
Programming Manual
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... Access MSR Addres s Size (bits) Description RW_NA 0x0E9E 64 R-Box Port 7 Mask 2 RW_NA 0x0E9D 64 R-Box Port 7 Match 2 RW_NA 0x0E9C 64 R-Box Port 7 Mask/Match Config 2 RW_NA 0x0E8E 64 R-Box Port 7 Mask 1 RW_NA 0x0E8D 64 R-Box Port 7 Match 1 RW_NA 0x0E8C 64 R-Box Port 7 Mask/Match .... INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 3) Pick a generic counter (control+data) that can be configured to monitor events) and the overflow bit(s) has been cleared, the R-Box is set the generic control to point to selected cores when...
... Access MSR Addres s Size (bits) Description RW_NA 0x0E9E 64 R-Box Port 7 Mask 2 RW_NA 0x0E9D 64 R-Box Port 7 Match 2 RW_NA 0x0E9C 64 R-Box Port 7 Mask/Match Config 2 RW_NA 0x0E8E 64 R-Box Port 7 Mask 1 RW_NA 0x0E8D 64 R-Box Port 7 Match 1 RW_NA 0x0E8C 64 R-Box Port 7 Mask/Match .... INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 3) Pick a generic counter (control+data) that can be configured to monitor events) and the overflow bit(s) has been cleared, the R-Box is set the generic control to point to selected cores when...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name R_MSR_PMON_CTR13 R_MSR_PMON_CTL13 R_MSR_PMON_CTR12 R_MSR_PMON_CTL12 R_MSR_PMON_CTR11 R_MSR_PMON_CTL11 R_MSR_PMON_CTR10 R_MSR_PMON_CTL10 R_MSR_PMON_CTR9 R_MSR_PMON_CTL9 R_MSR_PMON_CTR8 R_MSR_PMON_CTL8 Access MSR Addres s Size (bits) Description RW_RW 0x0E3B 64 R-Box PMON Counter 13 RW_NA 0x0E3A 64 R-Box PMON Control 13 RW_RW 0x0E39 64 R-Box PMON Counter 12 RW_NA 0x0E38 64 R-Box...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name R_MSR_PMON_CTR13 R_MSR_PMON_CTL13 R_MSR_PMON_CTR12 R_MSR_PMON_CTL12 R_MSR_PMON_CTR11 R_MSR_PMON_CTL11 R_MSR_PMON_CTR10 R_MSR_PMON_CTL10 R_MSR_PMON_CTR9 R_MSR_PMON_CTL9 R_MSR_PMON_CTR8 R_MSR_PMON_CTL8 Access MSR Addres s Size (bits) Description RW_RW 0x0E3B 64 R-Box PMON Counter 13 RW_NA 0x0E3A 64 R-Box PMON Control 13 RW_RW 0x0E39 64 R-Box PMON Counter 12 RW_NA 0x0E38 64 R-Box...
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name R_MSR_PMON_CTR1 R_MSR_PMON_CTL1 R_MSR_PMON_CTR0 R_MSR_PMON_CTL0 Access MSR Addres s Size (bits) Description RW_RW 0x0E13 64 R-Box PMON Counter 1 RW_NA 0x0E12 64 R-Box PMON Control 1 RW_RW 0x0E11 64 R-Box PMON Counter 0 RW_NA 0x0E10 64 R-Box PMON Control 0 R_MSR_PORT3_QLX_CFG R_MSR_PORT2_QLX_CFG R_MSR_PORT1_QLX_CFG R_MSR_PORT0_QLX_CFG R_MSR_PORT7_IPERF_CFG0 R_MSR_PORT6_IPERF_CFG0 R_MSR_PORT5_IPERF_CFG0 R_MSR_PORT4_IPERF_CFG0 R_MSR_PORT3_IPERF_CFG0...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name R_MSR_PMON_CTR1 R_MSR_PMON_CTL1 R_MSR_PMON_CTR0 R_MSR_PMON_CTL0 Access MSR Addres s Size (bits) Description RW_RW 0x0E13 64 R-Box PMON Counter 1 RW_NA 0x0E12 64 R-Box PMON Control 1 RW_RW 0x0E11 64 R-Box PMON Counter 0 RW_NA 0x0E10 64 R-Box PMON Control 0 R_MSR_PORT3_QLX_CFG R_MSR_PORT2_QLX_CFG R_MSR_PORT1_QLX_CFG R_MSR_PORT0_QLX_CFG R_MSR_PORT7_IPERF_CFG0 R_MSR_PORT6_IPERF_CFG0 R_MSR_PORT5_IPERF_CFG0 R_MSR_PORT4_IPERF_CFG0 R_MSR_PORT3_IPERF_CFG0...
Programming Manual
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING To use by PMUs. 0x0 Read zero; Must write to 1. b) Program the match/mask regs (see Table 2-50, "R_MSR_PORT{7-0}_XBR_SET{2-1}_MM_CFG Registers") .dis field (bit 63) to 0 and .mm_trig_en (bit 21) to 0 else behavior is undefined. 0x0...20 19:16 15:8 7:0 0x0 Disable; Ex: Set to '0001' to match on first flit. 0x0 upper 8 bits [71:64] of match data 0x0 upper 8 bits [71:64] of mask data The following table contains the packet traffic that can be monitored if one of flit count in a ...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING To use by PMUs. 0x0 Read zero; Must write to 1. b) Program the match/mask regs (see Table 2-50, "R_MSR_PORT{7-0}_XBR_SET{2-1}_MM_CFG Registers") .dis field (bit 63) to 0 and .mm_trig_en (bit 21) to 0 else behavior is undefined. 0x0...20 19:16 15:8 7:0 0x0 Disable; Ex: Set to '0001' to match on first flit. 0x0 upper 8 bits [71:64] of match data 0x0 upper 8 bits [71:64] of mask data The following table contains the packet traffic that can be monitored if one of flit count in a ...
Programming Manual
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The metric DRS.AnyResp - A 9 flit NCB message contains a full 64 byte cache line. 0x1F00 Any Non-Coherent Bypass message that is 9 flits in length. NOTE: Bits 71:16 of the R-Box's ports (NEW_PACKETS_RECV) , raw flit traffic (i.e. The AnyDataC messages are only ... that fail arbitration (GLOBAL_ARB_BID_FAIL), tracking status of a cache line in response to a core request. Also the match/mask configuration register should be either partial data or an interrupt. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-53.
The metric DRS.AnyResp - A 9 flit NCB message contains a full 64 byte cache line. 0x1F00 Any Non-Coherent Bypass message that is 9 flits in length. NOTE: Bits 71:16 of the R-Box's ports (NEW_PACKETS_RECV) , raw flit traffic (i.e. The AnyDataC messages are only ... that fail arbitration (GLOBAL_ARB_BID_FAIL), tracking status of a cache line in response to a core request. Also the match/mask configuration register should be either partial data or an interrupt. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING Table 2-53.
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INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7.4 M-BOX Performance Monitors Table 2-63. M-Box Performance Monitoring MSRs MSR Name MB1_CR_M_MSR_PMU_ADDR_MASK MB1_CR_M_MSR_PMU_ADDR_MATCH MB1_CR_M_MSR_PMU_MM_CFG Access MSR Address Size (bits) Description RW_RW 0x0E5E 64 M-Box 1 PMON Addr Mask RW_RW 0x0E5D 64 M-Box 1 PMON Addr Match RW_RW 0xCE5C 64 M-Box 1 PMON Mask/Match Config MB0_CR_M_MSR_PMU_ADDR_MASK MB0_CR_M_MSR_PMU_ADDR_MATCH...
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.7.4 M-BOX Performance Monitors Table 2-63. M-Box Performance Monitoring MSRs MSR Name MB1_CR_M_MSR_PMU_ADDR_MASK MB1_CR_M_MSR_PMU_ADDR_MATCH MB1_CR_M_MSR_PMU_MM_CFG Access MSR Address Size (bits) Description RW_RW 0x0E5E 64 M-Box 1 PMON Addr Mask RW_RW 0x0E5D 64 M-Box 1 PMON Addr Match RW_RW 0xCE5C 64 M-Box 1 PMON Mask/Match Config MB0_CR_M_MSR_PMU_ADDR_MASK MB0_CR_M_MSR_PMU_ADDR_MATCH...
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... must set the corresponding bits in the M-Box. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name MB0_CR_M_MSR_PMU_CNT_4 MB0_CR_M_MSR_PMU_CNT_CTL_4 MB0_CR_M_MSR_PMU_CNT_3 MB0_CR_M_MSR_PMU_CNT_CTL_3 MB0_CR_M_MSR_PMU_CNT_2 MB0_CR_M_MSR_PMU_CNT_CTL_2 MB0_CR_M_MSR_PMU_CNT_1 MB0_CR_M_MSR_PMU_CNT_CTL_1 MB0_CR_M_MSR_PMU_CNT_0 MB0_CR_M_MSR_PMU_CNT_CTL_0 Access MSR Address Size (bits) Description RW_RW 0x0CB9 64 M-Box 0 PMON Counter 4 RW_RW 0x0CB8 64 M-Box 0 PMON Control 4 RW_RW 0x0CB7 64 M-Box 0 PMON Counter...
... must set the corresponding bits in the M-Box. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING MSR Name MB0_CR_M_MSR_PMU_CNT_4 MB0_CR_M_MSR_PMU_CNT_CTL_4 MB0_CR_M_MSR_PMU_CNT_3 MB0_CR_M_MSR_PMU_CNT_CTL_3 MB0_CR_M_MSR_PMU_CNT_2 MB0_CR_M_MSR_PMU_CNT_CTL_2 MB0_CR_M_MSR_PMU_CNT_1 MB0_CR_M_MSR_PMU_CNT_CTL_1 MB0_CR_M_MSR_PMU_CNT_0 MB0_CR_M_MSR_PMU_CNT_CTL_0 Access MSR Address Size (bits) Description RW_RW 0x0CB9 64 M-Box 0 PMON Counter 4 RW_RW 0x0CB8 64 M-Box 0 PMON Control 4 RW_RW 0x0CB7 64 M-Box 0 PMON Counter...
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...and .rst_flag_sel to 0. 2.7.4.2 M-Box PMON state - The .en bit must also be cleared to use of these configuration registers is detected... Monitor Event List" for more details. M_MSR_PERF_GLOBAL_CTL Register Fields Bits HW Reset Val Description 5:0 0 Must be set to ... Register Fields Field clr_ov Bits HW Reset Val Description 5:0 0 Writing '1' to bit in filed causes corresponding bit in 'Overflow PerfMon Counter...bits include: - .pmi_en governs what to do if an overflow is to select the event to fully enable the counter. Table 2-65. INTEL® XEON® PROCESSOR...
...and .rst_flag_sel to 0. 2.7.4.2 M-Box PMON state - The .en bit must also be cleared to use of these configuration registers is detected... Monitor Event List" for more details. M_MSR_PERF_GLOBAL_CTL Register Fields Bits HW Reset Val Description 5:0 0 Must be set to ... Register Fields Field clr_ov Bits HW Reset Val Description 5:0 0 Writing '1' to bit in filed causes corresponding bit in 'Overflow PerfMon Counter...bits include: - .pmi_en governs what to do if an overflow is to select the event to fully enable the counter. Table 2-65. INTEL® XEON® PROCESSOR...
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...RW_RW RW_RW RW_RW RW_RW 0xC97 64 W-Box PMON Counter 3 0xC96 64 W-Box PMON Control 3 0xC95 64 W-Box PMON Counter 2 0xC94 64 W-Box PMON Control 2 0xC93 64 W-Box PMON Counter 1 0xC92 64 W-Box PMON Control 1 0xC91 64 W-Box PMON Counter 0 0xC90 64 W-Box PMON Control 0... data register can collect events. W_MSR_PMON_GLOBAL_CTL Register Fields Field fixed_en ig ctr_en Bits HW Reset Val Description 31 30:4 3:0 0 Enable the fixed counter 0 Read zero; INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.8.3 W-BOX Performance Monitors Table...
...RW_RW RW_RW RW_RW RW_RW 0xC97 64 W-Box PMON Counter 3 0xC96 64 W-Box PMON Control 3 0xC95 64 W-Box PMON Counter 2 0xC94 64 W-Box PMON Control 2 0xC93 64 W-Box PMON Counter 1 0xC92 64 W-Box PMON Control 1 0xC91 64 W-Box PMON Counter 0 0xC90 64 W-Box PMON Control 0... data register can collect events. W_MSR_PMON_GLOBAL_CTL Register Fields Field fixed_en ig ctr_en Bits HW Reset Val Description 31 30:4 3:0 0 Enable the fixed counter 0 Read zero; INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE UNCORE PERFORMANCE MONITORING 2.8.3 W-BOX Performance Monitors Table...