Specifications
Page 91
...through 17 define the timings associated with all phases of critical timing tDZFS 70 48 31 20 6.7 25 Time from STROBE output released-to-driving until the first transition of Ultra DMA data transfer. Figure 6-8 Initiating an Ultra DMA Read DMARQ (device) DMACK(host) STOP (host) ... 90 First strobe tUI 0 0 0 0 0 0 Unlimited interlock tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAD 0 0 0 0 0 0 Maximum delay time for output drivers turning on tENV tZIORDY 20 70 20 70 20 70 20 55 20 55 20 50 Envelope time 0 0 0 0 0 0...
...through 17 define the timings associated with all phases of critical timing tDZFS 70 48 31 20 6.7 25 Time from STROBE output released-to-driving until the first transition of Ultra DMA data transfer. Figure 6-8 Initiating an Ultra DMA Read DMARQ (device) DMACK(host) STOP (host) ... 90 First strobe tUI 0 0 0 0 0 0 Unlimited interlock tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAD 0 0 0 0 0 0 Maximum delay time for output drivers turning on tENV tZIORDY 20 70 20 70 20 70 20 55 20 55 20 50 Envelope time 0 0 0 0 0 0...
Specifications
Page 94
... interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect...(host) tSS DSTROBE (device) tLI tZAH tAZ tCVS tACK tIORDYZ tCVH DD(15:0) CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for output drivers turning on tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times...
... interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for the STOP, HDMARDY and DSTROBE signal lines are no longer in effect...(host) tSS DSTROBE (device) tLI tZAH tAZ tCVS tACK tIORDYZ tCVH DD(15:0) CRC tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for output drivers turning on tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times...
Specifications
Page 95
... interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to -pause time tIORDYZ 20 20 20 20 20 20 Maximum time before assertion and negation of DMACK_ K6602637 Rev.3 02.27.01 - 95 - Figure...) tRP tRFS tLI tAZ tMLI tZAH tMLI tLI tACK tACK tIO R D Y Z D D (1 5 :0 ) tCVS CRC tCVH tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for output drivers turning on tRFS 75 70 60 60 60 50 Ready-to-final-STROBE time tRP 160 125 100 100 100 85 Ready-to release tZAH...
... interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to -pause time tIORDYZ 20 20 20 20 20 20 Maximum time before assertion and negation of DMACK_ K6602637 Rev.3 02.27.01 - 95 - Figure...) tRP tRFS tLI tAZ tMLI tZAH tMLI tLI tACK tACK tIO R D Y Z D D (1 5 :0 ) tCVS CRC tCVH tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for output drivers turning on tRFS 75 70 60 60 60 50 Ready-to-final-STROBE time tRP 160 125 100 100 100 85 Ready-to release tZAH...
Specifications
Page 99
... interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to negation of DMARQ or assertion of STOP K6602637 Rev.3 02.27.01 - 99 - DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) Figure 6-16 Host...
... interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to negation of DMARQ or assertion of STOP K6602637 Rev.3 02.27.01 - 99 - DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) Figure 6-16 Host...