English manual.
Page 39
...appear in order. tCL The number of DRAM timing by SPD device. Otherwise, SPD value is a function of each DCT in AM2+ CPU) ► CAS Latency - DRAM Timing Configuration CMOS Setup Utility - Copyright (C) 1985-2005, American Megatrends, Inc. The...so that BIOS programs into the memory controller is selected. Settings are : [Auto]; [DCT 0]. (appear in AM2 CPU) Settings are enabled in clock cycles) between the CAS# and RAS# 32 Select [Auto] for SPD ...target clock frequency. The value that the motherboard memory controller (chipset) can better access the memory device.
...appear in order. tCL The number of DRAM timing by SPD device. Otherwise, SPD value is a function of each DCT in AM2+ CPU) ► CAS Latency - DRAM Timing Configuration CMOS Setup Utility - Copyright (C) 1985-2005, American Megatrends, Inc. The...so that BIOS programs into the memory controller is selected. Settings are : [Auto]; [DCT 0]. (appear in AM2 CPU) Settings are enabled in clock cycles) between the CAS# and RAS# 32 Select [Auto] for SPD ...target clock frequency. The value that the motherboard memory controller (chipset) can better access the memory device.