English Manual.
Page 9
1-1 Product Specifications 1 CPU Support AMD socket AM2+ PhenomTM X3 / PhenomTM X4 processors Support AMD socket AM2 series processors : AthlonTM 64X2 / AthlonTM 64 / SempronTM HyperTransport 2000/1600MT/s for AM2 CPU Up to 5200MT/s (HT3.0) for AM2+ CPU Chipset North Bridge: AMD 780V (A7VML, A7VML-K) AMD 760G (A76ML, A76ML-K) South Bridge: AMD SB700 (A7VML, A7VML-K) AMD SB710 (A76ML, A76ML-K) Memory 2 x 240-pin DDR2 DIMM sockets Support up...
1-1 Product Specifications 1 CPU Support AMD socket AM2+ PhenomTM X3 / PhenomTM X4 processors Support AMD socket AM2 series processors : AthlonTM 64X2 / AthlonTM 64 / SempronTM HyperTransport 2000/1600MT/s for AM2 CPU Up to 5200MT/s (HT3.0) for AM2+ CPU Chipset North Bridge: AMD 780V (A7VML, A7VML-K) AMD 760G (A76ML, A76ML-K) South Bridge: AMD SB700 (A7VML, A7VML-K) AMD SB710 (A76ML, A76ML-K) Memory 2 x 240-pin DDR2 DIMM sockets Support up...
English Manual.
Page 38
... after the read CAS_L is a function of memory clocks it takes a DRAM to Read Command Delay) 31 The target clock frequency is determined from the supported CAS latencies at given clock frequencies of each DCT in clock cycles) between the CAS# and RAS# strobe signals. ► TRP (Precharge Command Period) This... Delay) Internal READ Command to PRECHARGE Command delay. ► TRAS (Active-to-Precharge Delay) This item allows you to set the row cycle time (in AM2+ CPU. ► CAS Latency The number of the target clock frequency.
... after the read CAS_L is a function of memory clocks it takes a DRAM to Read Command Delay) 31 The target clock frequency is determined from the supported CAS latencies at given clock frequencies of each DCT in clock cycles) between the CAS# and RAS# strobe signals. ► TRP (Precharge Command Period) This... Delay) Internal READ Command to PRECHARGE Command delay. ► TRAS (Active-to-Precharge Delay) This item allows you to set the row cycle time (in AM2+ CPU. ► CAS Latency The number of the target clock frequency.