Aspire X1200 / X3200 Service Guide
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...8400/8450/8600/8650 processor T AMD Phenom X4 Quad-Core 9100e/9150e/9500/9550/9600/9650 processor T AMD Sempron LE-1250/1300 or 2100 processor Chipset T NVIDIA nForce MCP78 Memory subsystem T Supports up to two DDR2-667 registered ECC modules Media storage T DVD-ROM SATA drive T Super-Multi ...SATA DVD drive T 160 GB SATA hard disk drive Serial ATA controller T Embedded SATA2 controller T Two SATA ports Networking T One Gigabit Ethernet LAN port (RJ-45) PCI I/O T ...
...8400/8450/8600/8650 processor T AMD Phenom X4 Quad-Core 9100e/9150e/9500/9550/9600/9650 processor T AMD Sempron LE-1250/1300 or 2100 processor Chipset T NVIDIA nForce MCP78 Memory subsystem T Supports up to two DDR2-667 registered ECC modules Media storage T DVD-ROM SATA drive T Super-Multi ...SATA DVD drive T 160 GB SATA hard disk drive Serial ATA controller T Embedded SATA2 controller T Two SATA ports Networking T One Gigabit Ethernet LAN port (RJ-45) PCI I/O T ...
Aspire X1200 / X3200 Service Guide
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Setup Utility Menus The tabs on the Setup menu bar correspond to the six primary BIOS Setup menus, namely: T Product Information T Standard CMOS Features T Advanced BIOS Features T Advanced Chipset Features T Integrated Peripherals T Power Management Setup T PnP/PCI Configurations T PC Health Status T Load Default Settings T Set Supervisor Password T Set User Password T Save & Exit Setup T Exit Without Saving In the descriptive table following each of the menu screenshots, settings in boldface are the default and suggested settings. Chapter 2 9
Setup Utility Menus The tabs on the Setup menu bar correspond to the six primary BIOS Setup menus, namely: T Product Information T Standard CMOS Features T Advanced BIOS Features T Advanced Chipset Features T Integrated Peripherals T Power Management Setup T PnP/PCI Configurations T PC Health Status T Load Default Settings T Set Supervisor Password T Set User Password T Save & Exit Setup T Exit Without Saving In the descriptive table following each of the menu screenshots, settings in boldface are the default and suggested settings. Chapter 2 9
Aspire X1200 / X3200 Service Guide
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... cache. Advanced BIOS Features Parameter Description Option CPU Feature Press Enter to 80 tracks. On Off Gate A20 Option When set to fast, the motherboard chipset controls the operation of Gate A20. Fast Normal Typematic Rate Setting When enabled, you have 40 Disabled to configure the CPU Virtualization and AMD K8...
... cache. Advanced BIOS Features Parameter Description Option CPU Feature Press Enter to 80 tracks. On Off Gate A20 Option When set to fast, the motherboard chipset controls the operation of Gate A20. Fast Normal Typematic Rate Setting When enabled, you have 40 Disabled to configure the CPU Virtualization and AMD K8...
Aspire X1200 / X3200 Service Guide
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...Spread Spectrum SATA Spread Spectrum Description Option Enable or disable the Scalable Link Interface (SLI) technology. When set to disabled, the chipset disables any modulation of system memory allocated solely for the onboard graphics controller. Disabled Enabled When set to the Northbridge link bandwidth. ...Auto 200, 400, 600, 800 MHz, 1 GHz Controls the processor to down spread, the chipset modulates the SATA bus' baseline signal downwards by modulating the signals it generates so that the spikes are reduced to the Northbridge HT ...
...Spread Spectrum SATA Spread Spectrum Description Option Enable or disable the Scalable Link Interface (SLI) technology. When set to disabled, the chipset disables any modulation of system memory allocated solely for the onboard graphics controller. Disabled Enabled When set to the Northbridge link bandwidth. ...Auto 200, 400, 600, 800 MHz, 1 GHz Controls the processor to down spread, the chipset modulates the SATA bus' baseline signal downwards by modulating the signals it generates so that the spikes are reduced to the Northbridge HT ...
Aspire X1200 / X3200 Service Guide
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...07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h POST Routine Description Test CMOS R/W functionality Early chipset initialization T Disable shadow RAM T Disable L2 cache (socket 7 or below) T Program basic chipset registers Detect memory T Auto-detection of DRAM size, type, and ECC T Auto-detection of L2 cache ...(socket 7 or below) Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 and F000 shadow RAM Expand the X group codes locating in physical address 1000:0 Reserved Initial Superio_Earl_Init switch Reserved 1 Blank out screen 2 ...
...07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h POST Routine Description Test CMOS R/W functionality Early chipset initialization T Disable shadow RAM T Disable L2 cache (socket 7 or below) T Program basic chipset registers Detect memory T Auto-detection of DRAM size, type, and ECC T Auto-detection of L2 cache ...(socket 7 or below) Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 and F000 shadow RAM Expand the X group codes locating in physical address 1000:0 Reserved Initial Superio_Earl_Init switch Reserved 1 Blank out screen 2 ...
Aspire X1200 / X3200 Service Guide
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... invalid value for a valid VGA device & VGA BIOS, and put it into C000:0 1 If Early_Init_Onboard_Generator is valid, take into chipset. a value of 5Ah is defined. Early PCI Initialization: T Enumerate PCI bus number T Assign memory & I/O resource T Search for... RTC minute. 2 Load CMOS settings into BIOS stack. Reserved Reserved Initial interrupts vector table. Reserved Initial EARLY_PM_INIT switch. Chipset default values are directed to SPURIOUS_INT_HDLR & S/W interrupts to CMOS setup. Disable respective clock resource to empty PCI & DIMM slots. 2 ...
... invalid value for a valid VGA device & VGA BIOS, and put it into C000:0 1 If Early_Init_Onboard_Generator is valid, take into chipset. a value of 5Ah is defined. Early PCI Initialization: T Enumerate PCI bus number T Assign memory & I/O resource T Search for... RTC minute. 2 Load CMOS settings into BIOS stack. Reserved Reserved Initial interrupts vector table. Reserved Initial EARLY_PM_INIT switch. Chipset default values are directed to SPURIOUS_INT_HDLR & S/W interrupts to CMOS setup. Disable respective clock resource to empty PCI & DIMM slots. 2 ...
Aspire X1200 / X3200 Service Guide
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... the combined Trend Anti-Virus code Reserved (Optional Feature) Show message for function call: INT 15h ax=E820h Reserved Turn on L2 cache Reserved Program chipset registers according to items described in 40:hardware Reserved Reserved Reserved Reserved Reserved Detect & install all ISA PnP devices. 2 Auto assign ports to onboard COM...
... the combined Trend Anti-Virus code Reserved (Optional Feature) Show message for function call: INT 15h ax=E820h Reserved Turn on L2 cache Reserved Program chipset registers according to items described in 40:hardware Reserved Reserved Reserved Reserved Reserved Detect & install all ISA PnP devices. 2 Auto assign ports to onboard COM...
Aspire X1200 / X3200 Service Guide
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... occur, report errors & wait for keys T If no errors occur or F1 key is pressed to continue: T Clear EPA or customization logo Reserved Reserved 1 Call chipset power management hook 2 Recover the text fond used by EPA logo (not for full screen logo) 3 If password is set, ask for Trend Anti-Virus...
... occur, report errors & wait for keys T If no errors occur or F1 key is pressed to continue: T Clear EPA or customization logo Reserved Reserved 1 Call chipset power management hook 2 Recover the text fond used by EPA logo (not for full screen logo) 3 If password is set, ask for Trend Anti-Virus...
Aspire X1200 / X3200 Service Guide
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POST Code (Hex) 94h 95h 96h FFh POST Routine Description 1 Enable L2 cache 2 Program Daylight Saving 3 Program boot up speed 4 Chipset final initialization 5 Power management final initialization 6 Clear screen & display summary table 7 Program K6 write allocation 8 Program P6 class write combining Update keyboard LED & typematic rate 1 Build MP table 2 Build & update ESCD 3 Set CMOS century to 20h or 19h 4 Load CMOS time into DOS timer tick 5 Build MSIRQ routing table Boot attempt (INT 19h) 66 Chapter 4
POST Code (Hex) 94h 95h 96h FFh POST Routine Description 1 Enable L2 cache 2 Program Daylight Saving 3 Program boot up speed 4 Chipset final initialization 5 Power management final initialization 6 Clear screen & display summary table 7 Program K6 write allocation 8 Program P6 class write combining Update keyboard LED & typematic rate 1 Build MP table 2 Build & update ESCD 3 Set CMOS century to 20h or 19h 4 Load CMOS time into DOS timer tick 5 Build MSIRQ routing table Boot attempt (INT 19h) 66 Chapter 4