Service Guide
Page 113
... event registers Setup DRAM control register for normal operation and enable Enable RCOMP Clear DRAM initialization bit in the SB Initialization Sequence Completed, program graphic clocks Disable access to the XMM registers BDS & Specific action: Code 0x00 0x12 0x13 0x21 0x27 0x28 0x50 0x51 0x58 0x5A 0x70 0x71...memory range do the hard ware ECC init Report status code of every memory range Get the root bridge handle Notify pci bus driver starts to program the resource Reset the host controller IdeBus begin initialization Simple Text Output Protocol Functions (VGA class reset) Report that VGA...
... event registers Setup DRAM control register for normal operation and enable Enable RCOMP Clear DRAM initialization bit in the SB Initialization Sequence Completed, program graphic clocks Disable access to the XMM registers BDS & Specific action: Code 0x00 0x12 0x13 0x21 0x27 0x28 0x50 0x51 0x58 0x5A 0x70 0x71...memory range do the hard ware ECC init Report status code of every memory range Get the root bridge handle Notify pci bus driver starts to program the resource Reset the host controller IdeBus begin initialization Simple Text Output Protocol Functions (VGA class reset) Report that VGA...