User Manual
Page 89
DRAM Performance Mode Choose high performance mode can increase memory performance, but you might lose stability. CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in checkboxes. DRAM Configuration DRAM Tweaker Fine tune... of memory and accessing columns within it. and assign the appropriate frequency automatically. RAS# to confirm and apply your new settings. Click OK to CAS# Delay (tRCD) The number of clock cycles required between the issuing of the precharge command and opening of a row of clock cycles required between...
DRAM Performance Mode Choose high performance mode can increase memory performance, but you might lose stability. CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in checkboxes. DRAM Configuration DRAM Tweaker Fine tune... of memory and accessing columns within it. and assign the appropriate frequency automatically. RAS# to confirm and apply your new settings. Click OK to CAS# Delay (tRCD) The number of clock cycles required between the issuing of the precharge command and opening of a row of clock cycles required between...
User Manual
Page 90
... (tFAW) The time window in different banks of clocks from a Refresh command until the first Activate command to the same internal bank. Z97M OC Formula RAS# Active Time (tRAS) The number of one refresh command internally once it enters Self-Refresh mode. 83 English Refresh Cycle Time (... to a row precharge command to RAS Delay (tRRD) The number of clocks between a read command to the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. RAS to the same rank. tCKE Configure the period of time the DDR3 initiates a minimum of clock cycles required between when...
... (tFAW) The time window in different banks of clocks from a Refresh command until the first Activate command to the same internal bank. Z97M OC Formula RAS# Active Time (tRAS) The number of one refresh command internally once it enters Self-Refresh mode. 83 English Refresh Cycle Time (... to a row precharge command to RAS Delay (tRRD) The number of clocks between a read command to the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. RAS to the same rank. tCKE Configure the period of time the DDR3 initiates a minimum of clock cycles required between when...