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... provided herein. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability with respect to the operation or use of AMD hardware, software or other products and documentation described herein, for any act or omission of AMD concerning such products or this documentation, for any interruption of service, loss or interruption of...
... provided herein. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability with respect to the operation or use of AMD hardware, software or other products and documentation described herein, for any act or omission of AMD concerning such products or this documentation, for any interruption of service, loss or interruption of...
Revision History
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... Operators...8 Table 2. CPUID Values for AMD Family 15h Models 00h-0Fh C32r1 Processor Revisions 9 Table 4. CPUID Values for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions 10 Table 5. Cross Reference of Product Revision to Processor Segments...21 4 List of Tables Supported Mixed Revision Configurations...11 Table 6. Revision Guide for AMD Family 15h Models 00h-0Fh G34r1 Processor Revisions 9 Table 3. Cross-Reference...
... Operators...8 Table 2. CPUID Values for AMD Family 15h Models 00h-0Fh C32r1 Processor Revisions 9 Table 4. CPUID Values for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions 10 Table 5. Cross Reference of Product Revision to Processor Segments...21 4 List of Tables Supported Mixed Revision Configurations...11 Table 6. Revision Guide for AMD Family 15h Models 00h-0Fh G34r1 Processor Revisions 9 Table 3. Cross-Reference...
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.... Updated errata #534 and #671. Added Table 2 and Table 3. Added Mixed Processor Revision Support. ...AMD Opteron™ 4200 Series Processor and AMD Opteron™ 6200 Series Processor to Table 8. 48063 Rev. 3.18 October 2012 Revision History Revision Guide for AMD Family 15h Models 00h-0Fh Processors...Processors and OR-C0 silicon revision to Overview, Table 4, and Table 9; Added errata #685, #699, #704, #707, #708, #727, #734, #739, and #759. Removed erratum #534 as this is redundant with, and replaced by, errata #717 and #718; and #745; Added AMD Opteron™ 3200 Series Processor...
.... Updated errata #534 and #671. Added Table 2 and Table 3. Added Mixed Processor Revision Support. ...AMD Opteron™ 4200 Series Processor and AMD Opteron™ 6200 Series Processor to Table 8. 48063 Rev. 3.18 October 2012 Revision History Revision Guide for AMD Family 15h Models 00h-0Fh Processors...Processors and OR-C0 silicon revision to Overview, Table 4, and Table 9; Added errata #685, #699, #704, #707, #708, #727, #734, #739, and #759. Removed erratum #534 as this is redundant with, and replaced by, errata #717 and #718; and #745; Added AMD Opteron™ 3200 Series Processor...
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... specifications. • Documentation Support provides a listing of available technical support resources. This revision guide includes information on the following products: • AMD FX™-Series Processor • AMD Opteron™ 3200 Series Processor • AMD Opteron™ 3300 Series Processor • AMD Opteron™ 4200 Series Processor • AMD Opteron™ 4300 Series Processor • AMD Opteron™ 6200 Series Processor • AMD Opteron™ 6300 Series Processor This guide...
... specifications. • Documentation Support provides a listing of available technical support resources. This revision guide includes information on the following products: • AMD FX™-Series Processor • AMD Opteron™ 3200 Series Processor • AMD Opteron™ 3300 Series Processor • AMD Opteron™ 4200 Series Processor • AMD Opteron™ 4300 Series Processor • AMD Opteron™ 6200 Series Processor • AMD Opteron™ 6300 Series Processor This guide...
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...instruction function 8000_0001h. • MSRXXXX_XXXX: model specific registers; For example, D18F2x9C_x1C specifies the port 1Ch register accessed using the data port register at bus 0; 48063 Rev. 3.18 October 2012 Revision Guide for access properties. Some registers in the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301. Y specifies the function number...programmed into MSRC001_020[A,8,6,4,2,0][EventSelect] (PERF_CTL[5:0] bits 7:0). For example, CPUID Fn8000_0001_EAX refers to 7 digits) in numbers. The mnemonics for this space is...
...instruction function 8000_0001h. • MSRXXXX_XXXX: model specific registers; For example, D18F2x9C_x1C specifies the port 1Ch register accessed using the data port register at bus 0; 48063 Rev. 3.18 October 2012 Revision Guide for access properties. Some registers in the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301. Y specifies the function number...programmed into MSRC001_020[A,8,6,4,2,0][EventSelect] (PERF_CTL[5:0] bits 7:0). For example, CPUID Fn8000_0001_EAX refers to 7 digits) in numbers. The mnemonics for this space is...
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...bit result. ^ Bitwise exclusive-OR operator; Each set of registers. sometimes used as "raised to identify a range of bits is a shorthand notation for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 • NBPMCxXXX[Y]: northbridge performance monitor events; E.g. (!10b == 0b); Many register references use... number programmed into MSRC001_024[6,4,2,0][UnitMask] (NB_PERF_CTL[3:0] bits 15:8). E.g. (01b ^ 10b == 11b). E.g. (01b || 10b == 1b); E.g. (01b & 10b == 00b). && Logical AND operator. E.g., {Addr[3:2], Xlate[3:0]} represents a 6-bit value...
...bit result. ^ Bitwise exclusive-OR operator; Each set of registers. sometimes used as "raised to identify a range of bits is a shorthand notation for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 • NBPMCxXXX[Y]: northbridge performance monitor events; E.g. (!10b == 0b); Many register references use... number programmed into MSRC001_024[6,4,2,0][UnitMask] (NB_PERF_CTL[3:0] bits 15:8). E.g. (01b ^ 10b == 11b). E.g. (01b || 10b == 1b); E.g. (01b & 10b == 00b). && Logical AND operator. E.g., {Addr[3:2], Xlate[3:0]} represents a 6-bit value...
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... 9 Figure 1. Revision Determination A processor revision is identified using a unique value that is returned in D18F4x164 Fixed Errata Register (see D18F4x164 Fixed Errata Register). Table 2. Format of CPUID Fn0000_0001_EAX The following tables show the identification numbers from CPUID Fn0000_0001_EAX. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Processor Identification This section shows...
... 9 Figure 1. Revision Determination A processor revision is identified using a unique value that is returned in D18F4x164 Fixed Errata Register (see D18F4x164 Fixed Errata Register). Table 2. Format of CPUID Fn0000_0001_EAX The following tables show the identification numbers from CPUID Fn0000_0001_EAX. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Processor Identification This section shows...
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... specified bit to enable software to identify the applicability of a processor family is 0000001h. AMD Opteron™ 4200 Series Processor AMD Opteron™ 4300 Series Processor Revision Guide for the presence of the erratum. CPUID Values for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions CPUID Fn0000_0001_EAX, D18F4x164[1:0] AMD FX™ Series Processor AMD Opteron™ 3200 Series Processor AMD Opteron™ 3300 Series Processor 00600F12h...
... specified bit to enable software to identify the applicability of a processor family is 0000001h. AMD Opteron™ 4200 Series Processor AMD Opteron™ 4300 Series Processor Revision Guide for the presence of the erratum. CPUID Values for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions CPUID Fn0000_0001_EAX, D18F4x164[1:0] AMD FX™ Series Processor AMD Opteron™ 3200 Series Processor AMD Opteron™ 3300 Series Processor 00600F12h...
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... 48 bytes contained in a multiprocessor system. Refer to the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301 , for example a G34r1 processor can not be mixed in the six 64-bit registers of "AMD Unprogrammed Engineering Sample" and skip the remaining steps. 2. The processor name string is common practice for the 48-character...
... 48 bytes contained in a multiprocessor system. Refer to the BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h Models 00h-0Fh Processors, order# 42301 , for example a G34r1 processor can not be mixed in the six 64-bit registers of "AMD Unprogrammed Engineering Sample" and skip the remaining steps. 2. The processor name string is common practice for the 48-character...
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...Reserved. BIOS shall program the state of the valid status bits as defined in AMD64 Architecture Programmer's Manual Volume 2: System Programming, order# 24593, is not necessary. Cross Reference of Product Revision to the bit position within the OS Visible Work-around MSR0 (OSVW_ID_Length) ... to hand-off to specify the number of valid status bits within the valid status field. The reset default value of this register is 0000_0000_0000_0000h. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Operating System Visible Workarounds This section ...
...Reserved. BIOS shall program the state of the valid status bits as defined in AMD64 Architecture Programmer's Manual Volume 2: System Programming, order# 24593, is not necessary. Cross Reference of Product Revision to the bit position within the OS Visible Work-around MSR0 (OSVW_ID_Length) ... to hand-off to specify the number of valid status bits within the valid status field. The reset default value of this register is 0000_0000_0000_0000h. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Operating System Visible Workarounds This section ...
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...Errors May Lead to Errata CPUID Fn0000_0001_EAX, D18F4x164[1:0] No. Note: There may have been deleted or renumbered. A unique tracking number for user convenience in tracking the errata within specific revision levels. In addition, errata that have been resolved from early revisions of the processor. Table 7. Revision Guide for AMD Family 15h Models 00h-0Fh Processors... 536 Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches 537 Performance Counter for Ineffective Software Prefetches Does Not Count for L2 Hits 538 Performance Counter ...
...Errors May Lead to Errata CPUID Fn0000_0001_EAX, D18F4x164[1:0] No. Note: There may have been deleted or renumbered. A unique tracking number for user convenience in tracking the errata within specific revision levels. In addition, errata that have been resolved from early revisions of the processor. Table 7. Revision Guide for AMD Family 15h Models 00h-0Fh Processors... 536 Performance Counter for Instruction Cache Misses Does Not Increment for Sequential Prefetches 537 Performance Counter for Ineffective Software Prefetches Does Not Count for L2 Hits 538 Performance Counter ...
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... for AMD Family 15h Models 00h-0Fh Processors Table 7. Cross-Reference of Processor Revision to SMI 673 Misaligned Page Crossing String Operations May Cause System Hang 674 Processor May Cache Prefetched Data from Remapped Memory Region 675 Instructions Performing Read-Modify-Write May Alter Architectural State Before #PF 685 Some Processor Cores May Have Inaccurate Instruction Cache Fetch Performance Counter 689 AM3r2 Six Core Processor May...
... for AMD Family 15h Models 00h-0Fh Processors Table 7. Cross-Reference of Processor Revision to SMI 673 Misaligned Page Crossing String Operations May Cause System Hang 674 Processor May Cache Prefetched Data from Remapped Memory Region 675 Instructions Performing Read-Modify-Write May Alter Architectural State Before #PF 685 Some Processor Cores May Have Inaccurate Instruction Cache Fetch Performance Counter 689 AM3r2 Six Core Processor May...
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...Boundaries 727 Processor Core May Hang During CC6 Resume 734 Processor May Incorrectly Store VMCB Data 737 Processor Does Not Check 128-bit Canonical Address Boundary Case on Logical Address 739 Processor May Read Branch Status Register With Inconsistent Parity Bit 740 Lightweight...of Instruction Fetches May Be Uneven 695 Processor May Interpret FCW Incorrectly after FNSAVE/ FSAVE Limit Fault 699 Processor May Generate Illegal Access in VMLOAD or VMSAVE Instruction 704 Processor May Report Incorrect Instruction Pointer 707 Performance Counter for AMD Family 15h Models 00h-0Fh Processors 48063 ...
...Boundaries 727 Processor Core May Hang During CC6 Resume 734 Processor May Incorrectly Store VMCB Data 737 Processor Does Not Check 128-bit Canonical Address Boundary Case on Logical Address 739 Processor May Read Branch Status Register With Inconsistent Parity Bit 740 Lightweight...of Instruction Fetches May Be Uneven 695 Processor May Interpret FCW Incorrectly after FNSAVE/ FSAVE Limit Fault 699 Processor May Generate Illegal Access in VMLOAD or VMSAVE Instruction 704 Processor May Report Incorrect Instruction Pointer 707 Performance Counter for AMD Family 15h Models 00h-0Fh Processors 48063 ...
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... 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Cross-Reference of the erratum, or it may not apply to a processor segment due to a specific characteristic of Errata to Processor Segments This table cross-references the errata to each processor segment. An erratum may be due to the affected silicon revision(s) not being used in this processor segment...
... 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors Cross-Reference of the erratum, or it may not apply to a processor segment due to a specific characteristic of Errata to Processor Segments This table cross-references the errata to each processor segment. An erratum may be due to the affected silicon revision(s) not being used in this processor segment...
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... October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 623 Small Code Segment Limits May Cause Incorrect Limit Faults Description In cases where the code segment limit is less than 32 bytes. Suggested Workaround None required. In the unlikely case that code segment sizes are greater than 0_0020h and the Granularity (G) bit is 32 bytes...
... October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 623 Small Code Segment Limits May Cause Incorrect Limit Faults Description In cases where the code segment limit is less than 32 bytes. Suggested Workaround None required. In the unlikely case that code segment sizes are greater than 0_0020h and the Granularity (G) bit is 32 bytes...
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... after checking for affected silicon family and model (CPUID Fn0000_0001_EAX[Extended Family, Family, Extended Model and Model]), and that the processor reports zero for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB Description The CPUID instruction incorrectly reports the number of entries and the associativity of...
... after checking for affected silicon family and model (CPUID Fn0000_0001_EAX[Extended Family, Family, Extended Model and Model]), and that the processor reports zero for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB Description The CPUID instruction incorrectly reports the number of entries and the associativity of...
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...0001b (AM3r2 package type). • CPUID Fn8000_0008_ECX[NC] (APIC ID Size and Core Count[Number of Physical Cores]) = 5. • D18F4x150[7:0] = 6Bh. • D18F4x10C[11:0] (TDP...parts, the following conditions should be met before implementing this workaround: • CC6 is enabled. Suggested Workaround AMD recommends that system software disables CC6, disable APM using Core Performance Boost Control Register[ApmMasterEn] (D18F4x15C[7]) = 0b. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 689 AM3r2 Six Core Processor May Limit P-State When Core...
...0001b (AM3r2 package type). • CPUID Fn8000_0008_ECX[NC] (APIC ID Size and Core Count[Number of Physical Cores]) = 5. • D18F4x150[7:0] = 6Bh. • D18F4x10C[11:0] (TDP...parts, the following conditions should be met before implementing this workaround: • CC6 is enabled. Suggested Workaround AMD recommends that system software disables CC6, disable APM using Core Performance Boost Control Register[ApmMasterEn] (D18F4x15C[7]) = 0b. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 689 AM3r2 Six Core Processor May Limit P-State When Core...
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... required before this setting takes effect. Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 690 Northbridge FIFO Read/Write Pointer Overlap May Cause Hang or Protocol Error Machine Check Description A command or data transfer may also report a probe filter protocol machine check exception identified by the extended error code in the NB...
... required before this setting takes effect. Revision Guide for AMD Family 15h Models 00h-0Fh Processors 48063 Rev. 3.18 October 2012 690 Northbridge FIFO Read/Write Pointer Overlap May Cause Hang or Protocol Error Machine Check Description A command or data transfer may also report a probe filter protocol machine check exception identified by the extended error code in the NB...
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... processor cores that the instruction cache and the L2 cache as being shared between two processor cores. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 745 Processor May Incorrectly Report Cache Sharing Property in CPUID Topology Description On processor models that have a single core per compute-unit (Compute Unit Status Register[DualCore], D18F5x80[16] is 0b), CPUID Fn8000_001D_EAX_x1[NumSharingCache, bits...
... processor cores that the instruction cache and the L2 cache as being shared between two processor cores. 48063 Rev. 3.18 October 2012 Revision Guide for AMD Family 15h Models 00h-0Fh Processors 745 Processor May Incorrectly Report Cache Sharing Property in CPUID Topology Description On processor models that have a single core per compute-unit (Compute Unit Status Register[DualCore], D18F5x80[16] is 0b), CPUID Fn8000_001D_EAX_x1[NumSharingCache, bits...
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... • AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, order# 26569 • AMD CPUID Specification, order# 25481 • Advanced Platform Management Link (APML) Specification, order# 41918 • HyperTransport™ I/O Link Specification (www.hypertransport.org) • AMD I/O Virtualization Technology (IOMMU) Specification, order# 48882 See the AMD Web site at www.amd.com for the latest updates to documents. Documentation Support 91
... • AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, order# 26569 • AMD CPUID Specification, order# 25481 • Advanced Platform Management Link (APML) Specification, order# 41918 • HyperTransport™ I/O Link Specification (www.hypertransport.org) • AMD I/O Virtualization Technology (IOMMU) Specification, order# 48882 See the AMD Web site at www.amd.com for the latest updates to documents. Documentation Support 91
