AMD 3200 - Athlon 64 2.0 GHz Processor Support and Manuals
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AMD 3200 Videos
Lego:Lord Of The Rings On Single Core 3200+
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Duration: 7:59
Total Views: 106
Alan Wakes American Nightmare On Single Core AMD Athlon 3200+
Duration: 4:06
Total Views: 245
Duration: 4:06
Total Views: 245
Trine 2 On Single Core-AMD Athlon 3200+
Duration: 7:45
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Duration: 7:45
Total Views: 196
Borderlands 2 On Single Core AMD Athlon 3200+
Duration: 17:11
Total Views: 2,122
Duration: 17:11
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Popular AMD 3200 Manual Pages
Revision History - Page 4
...
48063 Rev. 3.18 October 2012
List of Processor Revision to Errata...14 Table 8. Supported Mixed Revision Configurations...11 Table 6. Cross-Reference of Tables
Table 1. Arithmetic and Logic Operators...8 Table 2. CPUID Values for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions 10 Table 5. Cross-Reference of Errata to Processor Segments...21
4
List of Errata to OSVW...
Revision History - Page 5
...AMD Family 15h Models 00h-0Fh Processors
Date October 2012 August 2012 May 2012
November 2011 October 2011
Revision 3.18 3.16 3.12
3.04 3.00
Description
Added AMD Opteron™ 3300 Series, 4300 Series, 6300 Series Processors and OR-C0 silicon revision to Overview and Tables 2-8. 48063 Rev. 3.18 October 2012
Revision History
Revision Guide for errata #724;
Added AMD Opteron™ 3200...
Revision History - Page 6
... support resources. This revision guide may cause the behavior of the processor to designers of computer systems and software developers.
An erratum is to communicate updated product information to deviate from published specifications. This revision guide includes information on system operation and suggested workarounds. Revision Guide for AMD Family 15h Models 00h-0Fh Processors...
Revision History - Page 8
For example, D18F2x[1,0][4C:40] is a shorthand notation for AMD Family 15h Models 00h-0Fh Processors
48063 Rev. 3.18 October 2012
• NBPMCxXXX[Y]: northbridge performance monitor events; Arithmetic and Logic Operators
Operator
Definition
{}
Curly brackets are used to the power of bits that are Xlate[3:0].
|
Bitwise OR operator. the two MSBs are Addr[3:2] and the...
Revision History - Page 10
... the workaround. Once defined, the definition of the status bit will persist within the family of a processor family is used to test for AMD Family 15h Models 00h-0Fh AM3r2 Processor Revisions
CPUID Fn0000_0001_EAX, D18F4x164[1:0]
AMD FX™ Series Processor AMD Opteron™ 3200 Series Processor AMD Opteron™ 3300 Series Processor
00600F12h, 1b (OR-B2) 00600F20h, 11b (OR-C0...
Revision History - Page 11
... in Table 5. 48063 Rev. 3.18 October 2012
Revision Guide for AMD Family 15h Models 00h-0Fh Processors
Mixed Processor Revision Support
AMD Family 15h processors with a C32r1 processor. Mixed revision support includes the AMD Opteron™ processor configurations as shown in the six 64-bit registers of how the 48-character processor name string maps to the six MSR addresses covered by...
Revision History - Page 13
...-around status registers.
48063 Rev. 3.18 October 2012
Revision Guide for AMD Family 15h Models 00h-0Fh Processors
Operating System Visible Workarounds
This section describes how to the bit position within the OS Visible Work-around MSR1 (OSVW_Status)
This register, as defined in AMD64 Architecture Programmer's Manual Volume 2: System Programming, order# 24593, provides the status of...
Revision History - Page 14
...)
361 Breakpoint Due to an Instruction That Has an Interrupt Shadow May Be Lost
503 APIC Task-Priority Register May Be Incorrect
504 Corrected L3 Errors May Lead to each erratum has been assigned within specific revision levels. Note: There may have been resolved from early revisions of the processor. Table 7.
A unique tracking number...
Revision History - Page 15
48063 Rev. 3.18 October 2012
Revision Guide for MCA Errors Within the CC6 Save Area
657 MC1_STATUS Enable Bit Not Set When Logging Corrected Errors
658 CPUID Incorrectly Reports Large Page Support in L2 Instruction TLB
659 VMCB Interrupt Shadow Status May Be Incorrect
660 APERF May Increase Unpredictably
661 P-State Limit and Stop Clock Assertion May Cause...
Revision History - Page 21
... specific characteristic of Errata to the affected silicon revision(s) not being used in this processor segment. Cross-Reference of Errata to Processor Segments
Processor Segment
Errata AMD FX ™ -Series Processor AMD Opteron ™ 3200 Processor AMD Opteron ™ 3300 Processor AMD Opteron ™ 4200 Processor AMD Opteron ™ 4300 Processor AMD Opteron ™ 6200 Processor AMD...
Revision History - Page 22
Cross-Reference of Errata to Processor Segments (continued)
Processor Segment
48063 Rev. 3.18 October 2012
Errata AMD FX ™ -Series Processor AMD Opteron ™ 3200 Processor AMD Opteron ™ 3300 Processor AMD Opteron ™ 4200 Processor AMD Opteron ™ 4300 Processor AMD Opteron ™ 6200 Processor AMD Opteron ™ 6300 Processor
658 X
X
X
X
659 X
X
X
X
660 X
X...
Revision History - Page 43
48063 Rev. 3.18 October 2012
Revision Guide for AMD Family 15h Models 00h-0Fh Processors
623 Small Code Segment Limits May Cause Incorrect Limit Faults
Description In cases where the code segment limit is less than 32 bytes. Fix Planned Yes
Product Errata
43 Suggested Workaround None required.
It is zero, the processor reports an incorrect #GP exception...
Revision History - Page 50
... Fn8000_0019_EBX[L2ITlb1GAssoc] = 6
This workaround should only be implemented after checking for affected silicon family and model (CPUID Fn0000_0001_EAX[Extended Family, Family, Extended Model and Model]), and that the processor reports zero for AMD Family 15h Models 00h-0Fh Processors
48063 Rev. 3.18 October 2012
658 CPUID Incorrectly Reports Large Page Support in the L2 instruction TLB.
Revision History - Page 89
... may incorrectly observe the topology of the instruction cache and the L2 cache. Fix Planned Yes
Product Errata
89 48063 Rev. 3.18 October 2012
Revision Guide for AMD Family 15h Models 00h-0Fh Processors
745 Processor May Incorrectly Report Cache Sharing Property in CPUID Topology
Description On processor models that have a single core per compute-unit (Compute Unit Status...
Revision History - Page 91
... 24593 • AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, order#
24594 • AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, order#
26568 • AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions,
order# 26569 • AMD CPUID Specification, order# 25481 •...
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