English Manual.
Page 9
...Dual-core/Celeron® processors Supports 45nm processors Front Side Bus 1600(oc*)/1333/1066/800MHz FSB (oc* : Overclocking) Chipset North Bridge : Intel® G31 Chipset South Bridge : Intel® ICH7 Memory 2 x 240-pin DDR2 DIMM sockets Support up to 4GB of ... Dual channel DDR2 800/667MHz architecture Audio Realtek 6-channel audio chip High Definition Audio 2/4/5.1-channel Support Jack-Sensing function LAN Realtek 10/100Mb/s LAN chip (G31MXP) Realtek Gigabit LAN chip (G31MXP-K) Expansion Slots 1 x PCI Express x1 slot 1 x PCI Express x16 slot 2 x...
...Dual-core/Celeron® processors Supports 45nm processors Front Side Bus 1600(oc*)/1333/1066/800MHz FSB (oc* : Overclocking) Chipset North Bridge : Intel® G31 Chipset South Bridge : Intel® ICH7 Memory 2 x 240-pin DDR2 DIMM sockets Support up to 4GB of ... Dual channel DDR2 800/667MHz architecture Audio Realtek 6-channel audio chip High Definition Audio 2/4/5.1-channel Support Jack-Sensing function LAN Realtek 10/100Mb/s LAN chip (G31MXP) Realtek Gigabit LAN chip (G31MXP-K) Expansion Slots 1 x PCI Express x1 slot 1 x PCI Express x16 slot 2 x...
English Manual.
Page 37
...) allows a platform to run multiple operating systems and applications in the buffer, the processor disables code execution, preventing damage and worm propagation. This item is used to enable/disable the C1E support. ► Execute Disable Bit This item is used to enable/disable it. 30 .... Vanderpool Technology can enable/disable the EIST (Processor Power Management, PPM) through this feature and the setting is used to enable or disable CPUID maximum value limit configuration. This item will be displayed only when the CPU is supporting this item. ! Intel's Execute Disable Bit ...
...) allows a platform to run multiple operating systems and applications in the buffer, the processor disables code execution, preventing damage and worm propagation. This item is used to enable/disable the C1E support. ► Execute Disable Bit This item is used to enable/disable it. 30 .... Vanderpool Technology can enable/disable the EIST (Processor Power Management, PPM) through this feature and the setting is used to enable or disable CPUID maximum value limit configuration. This item will be displayed only when the CPU is supporting this item. ! Intel's Execute Disable Bit ...
English Manual.
Page 48
.... ACPI defines five sleeping states, they are lost (CPU or chip set context are : S1 - Control starts from the processor's reset vector after the wake event. HPET Support [Enabled] HPET Mode [32-bit mode] USB Wake Up from a saved memory image. 41 Hardware maintains memory context and ...Resume by the OS (for maintaining the caches and CPU context). In other words, it is lost except system memory. Control starts from the processor's reset vector after the wake event. (also called Suspend to a minimum, it is a standard that the CPU and system cache context is ...
.... ACPI defines five sleeping states, they are lost (CPU or chip set context are : S1 - Control starts from the processor's reset vector after the wake event. HPET Support [Enabled] HPET Mode [32-bit mode] USB Wake Up from a saved memory image. 41 Hardware maintains memory context and ...Resume by the OS (for maintaining the caches and CPU context). In other words, it is lost except system memory. Control starts from the processor's reset vector after the wake event. (also called Suspend to a minimum, it is a standard that the CPU and system cache context is ...