Veriton 5800/6800/7800 Service Guide (Gigabyte MB)
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... List Hotkey c Function Enter BIOS Setup Utility Description Press while the system is booting to system installed with a Pentium 4 processor Tag RAM Location L2 Cache RAM Location L2 Cache RAM type L2 Cache RAM size L2 Cache RAM speed L2 Cache function control L2 Cache scheme On Processor On Processor PBSRAM (Pipelined-burst Synchronous... RAM) Depends on CPU, which is only applicable to enter BIOS Setup Utility. Specification VRM (Voltage Regulator Module) Function CPU VRM CPU VRM Cache ...
... List Hotkey c Function Enter BIOS Setup Utility Description Press while the system is booting to system installed with a Pentium 4 processor Tag RAM Location L2 Cache RAM Location L2 Cache RAM type L2 Cache RAM size L2 Cache RAM speed L2 Cache function control L2 Cache scheme On Processor On Processor PBSRAM (Pipelined-burst Synchronous... RAM) Depends on CPU, which is only applicable to enter BIOS Setup Utility. Specification VRM (Voltage Regulator Module) Function CPU VRM CPU VRM Cache ...
Veriton 5800/6800/7800 Service Guide (Gigabyte MB)
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... of chassis Adequate venting in the rear of chassis Memory Address Map Address 0000000 - 009FFFF 00A0000-00BFFFF Size 640 KB System Memory 128 KB Video RAM Function Onboard DRAM Reserved for Graphics Display Buffer Non-Cacheable Reserved for ROM on I/O Adapters Reserved for ROM on I/O Adapters Reserved for ROM on I/O Adapters...
... of chassis Adequate venting in the rear of chassis Memory Address Map Address 0000000 - 009FFFF 00A0000-00BFFFF Size 640 KB System Memory 128 KB Video RAM Function Onboard DRAM Reserved for Graphics Display Buffer Non-Cacheable Reserved for ROM on I/O Adapters Reserved for ROM on I/O Adapters Reserved for ROM on I/O Adapters...
Veriton 5800/6800/7800 Service Guide (Gigabyte MB)
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... Test (POST) is denoted by an unique check point number. Checkpoint CFh C0h Test CMOS R/W functionality Early chipset initialization: -Disable shadow RAM -Disable L2 cache (socket 7 or below) -Program basic chipset registers Detect memory -Auto-detection of DRAM size, type and ECC. ... numeric co-processor and cache memory subsystem Direct Memory Access (DMA) controller Interrupt system Three programmable timers ROM subsystem RAM subsystem CMOS RAM subsystem and real time clock/calendar with battery backup Onboard parallel interface controller Embedded hard disk interface and one diskette drive...
... Test (POST) is denoted by an unique check point number. Checkpoint CFh C0h Test CMOS R/W functionality Early chipset initialization: -Disable shadow RAM -Disable L2 cache (socket 7 or below) -Program basic chipset registers Detect memory -Auto-detection of DRAM size, type and ECC. ... numeric co-processor and cache memory subsystem Direct Memory Access (DMA) controller Interrupt system Three programmable timers ROM subsystem RAM subsystem CMOS RAM subsystem and real time clock/calendar with battery backup Onboard parallel interface controller Embedded hard disk interface and one diskette drive...
Veriton 5800/6800/7800 Service Guide (MSI MB)
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...Setup Utility. BIOS Hotkey List Hotkey c Function Enter BIOS Setup Utility Description Press while the system is local configured L2 Cache RAM speed Full of the processor core clock frequency (Advanced Transfer Cache) L2 Cache function control Enable/Disable by BIOS Setup Second... information below is only applicable to system installed with a Pentium 4 processor Tag RAM Location On Processor L2 Cache RAM Location On Processor L2 Cache RAM type PBSRAM (Pipelined-burst Synchronous RAM) L2 Cache RAM size Depends on CPU, which is booting to Error Correction Code (ECC) feature...
...Setup Utility. BIOS Hotkey List Hotkey c Function Enter BIOS Setup Utility Description Press while the system is local configured L2 Cache RAM speed Full of the processor core clock frequency (Advanced Transfer Cache) L2 Cache function control Enable/Disable by BIOS Setup Second... information below is only applicable to system installed with a Pentium 4 processor Tag RAM Location On Processor L2 Cache RAM Location On Processor L2 Cache RAM type PBSRAM (Pipelined-burst Synchronous RAM) L2 Cache RAM size Depends on CPU, which is booting to Error Correction Code (ECC) feature...
Veriton 5800/6800/7800 Service Guide (MSI MB)
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... 00A0000-00BFFFF 00C0000-00CFFFF 00D0000-00D3FFF 00D4000-00D7FFF 00D8000-00DBFFF 00DC000-00DFFFF 00E0000-00E7FFF 00E8000-00EFFFF 22 Size 640 KB System Memory 128 KB Video RAM 32 KB I/O Expansion ROM 16 KB I/O Expansion ROM 16 KB I/O Expansion ROM 16 KB I/O Expansion ROM 16 KB I/O Expansion ROM 32 KB for SCSI BIOS...
... 00A0000-00BFFFF 00C0000-00CFFFF 00D0000-00D3FFF 00D4000-00D7FFF 00D8000-00DBFFF 00DC000-00DFFFF 00E0000-00E7FFF 00E8000-00EFFFF 22 Size 640 KB System Memory 128 KB Video RAM 32 KB I/O Expansion ROM 16 KB I/O Expansion ROM 16 KB I/O Expansion ROM 16 KB I/O Expansion ROM 16 KB I/O Expansion ROM 32 KB for SCSI BIOS...
Veriton 5800/6800/7800 Service Guide (MSI MB)
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... co-processor and cache memory subsystem T Direct Memory Access (DMA) controller T Interrupt system T Three programmable timers T ROM subsystem T RAM subsystem T CMOS RAM subsystem and real time clock/calendar with built-in the table, refer to the corresponding product service guide. For other unique check point ...Detect memory -Auto-detection of DRAM size, type and ECC. -Auto-detection of preset numbers called check points to E000 & F000 shadow RAM. Post Checkpoints List: The list may vary accordingly depending on a debug board. This latch can be latched at port 80h, indicating the...
... co-processor and cache memory subsystem T Direct Memory Access (DMA) controller T Interrupt system T Three programmable timers T ROM subsystem T RAM subsystem T CMOS RAM subsystem and real time clock/calendar with built-in the table, refer to the corresponding product service guide. For other unique check point ...Detect memory -Auto-detection of DRAM size, type and ECC. -Auto-detection of preset numbers called check points to E000 & F000 shadow RAM. Post Checkpoints List: The list may vary accordingly depending on a debug board. This latch can be latched at port 80h, indicating the...
Veriton 5800/6800/7800 Service Guide (MSI MB)
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... data: NOTE: You can automatically boot OS every time it will damage the mainboard. 98 Chapter 5 Avoid clearing the CMOS while the system is a CMOS RAM on ; IEEE 1394 Connector: J1394_1 The mainboard provides one 1394 pin header that has a power supply from external battery to keep the system configuration data... system configuration, use the JBAT1 (Clear CMOS) Jumper to clear data. If you to connect optional IEEE 1394 port. it is off. With the CMOS RAM, the system can clear CMOS by shorting 2-3 pin while the system is turned on.
... data: NOTE: You can automatically boot OS every time it will damage the mainboard. 98 Chapter 5 Avoid clearing the CMOS while the system is a CMOS RAM on ; IEEE 1394 Connector: J1394_1 The mainboard provides one 1394 pin header that has a power supply from external battery to keep the system configuration data... system configuration, use the JBAT1 (Clear CMOS) Jumper to clear data. If you to connect optional IEEE 1394 port. it is off. With the CMOS RAM, the system can clear CMOS by shorting 2-3 pin while the system is turned on.
Veriton 5800/6800/7800 User"s Guide (EN)
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... Supporting up to 4 GB of DDR2 667 RAM Dual channels supported on four DIMMs Veriton 5800: • Two external 5.25" drive bays • Three 3.5" drive bays (two internal, one external) Veriton 6800: • Two external 5.25" drive bays • Six 3.5" drive bays (four internal, two external) Veriton 7800: • Three external 5.25" drive bays •...
... Supporting up to 4 GB of DDR2 667 RAM Dual channels supported on four DIMMs Veriton 5800: • Two external 5.25" drive bays • Three 3.5" drive bays (two internal, one external) Veriton 6800: • Two external 5.25" drive bays • Six 3.5" drive bays (four internal, two external) Veriton 7800: • Three external 5.25" drive bays •...