User Manual
Page 89
... the beginning of the data in checkboxes. DRAM Configuration DRAM Tweaker Fine tune the DRAM settings by leaving marks in response. CAS# Latency (tCL) The time between sending a column address to CAS# Delay (tRCD) The number of clock cycles required between the issuing of the precharge command and opening of a row of clock...
... the beginning of the data in checkboxes. DRAM Configuration DRAM Tweaker Fine tune the DRAM settings by leaving marks in response. CAS# Latency (tCL) The time between sending a column address to CAS# Delay (tRCD) The number of clock cycles required between the issuing of the precharge command and opening of a row of clock...
User Manual
Page 90
... the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. Write to Read Delay (tWTR) The number of clocks from a Refresh command until the first Activate command to the same rank. Z97M OC Formula RAS# Active...
... the same rank. CAS Write Latency (tCWL) Configure CAS Write Latency. Command Rate (CR) The delay between when a memory chip is selected and when the first active command can be issued. Write to Read Delay (tWTR) The number of clocks from a Refresh command until the first Activate command to the same rank. Z97M OC Formula RAS# Active...