Product Specification
Page 1
SAI2 Server Board Technical Product Specification Revision 1.0 November 2001 Enterprise Platforms and Services Marketing
SAI2 Server Board Technical Product Specification Revision 1.0 November 2001 Enterprise Platforms and Services Marketing
Product Specification
Page 3
... intended for conflicts or incompatibilities arising from published specifications. Copyright © Intel Corporation 2001. Intel reserves these for future definition and shall have no liability whatsoever, and Intel disclaims any features or instructions marked "reserved" or "undefined." Revision 1.0 iii The SAI2 Server Board may cause the product to specifications and product descriptions at any patent, copyright...
... intended for conflicts or incompatibilities arising from published specifications. Copyright © Intel Corporation 2001. Intel reserves these for future definition and shall have no liability whatsoever, and Intel disclaims any features or instructions marked "reserved" or "undefined." Revision 1.0 iii The SAI2 Server Board may cause the product to specifications and product descriptions at any patent, copyright...
Product Specification
Page 6
Baseboard Specifications 59 6.1 Estimated Baseboard MTBF 59 6.2 Absolute Maximum Ratings 60 6.3 Calculated Power Consumption 60 6.4 Measured Power Consumption 61 7. Table of Contents SAI2 Server Board TPS 4.3.12 USB Connectors (J2 53 4.3.13 IDE Connectors (PRI_IDE, SEC_IDE 53 4.3.14 32-Bit PCI Connectors 54 4.3.15 64-Bit PCI Connectors 55 4.3.16 Front Panel 24-pin Connector...
Baseboard Specifications 59 6.1 Estimated Baseboard MTBF 59 6.2 Absolute Maximum Ratings 60 6.3 Calculated Power Consumption 60 6.4 Measured Power Consumption 61 7. Table of Contents SAI2 Server Board TPS 4.3.12 USB Connectors (J2 53 4.3.13 IDE Connectors (PRI_IDE, SEC_IDE 53 4.3.14 32-Bit PCI Connectors 54 4.3.15 64-Bit PCI Connectors 55 4.3.16 Front Panel 24-pin Connector...
Product Specification
Page 11
... the JEDEC PC133 specification - CNB30LE North Bridge - Four DIMM slots allow a maxiumum installed memory of both primary and secondary processors • ServerWorks* ServerSet* III LE chipset - 133-MHz Front Side Bus (FSB) Capability - SAI2 Server Board TPS Introduction 1. Two 64-bit, 66-MHz..., 3.3-V keyed PCI expansion slots • 32-bit, 33-MHz, 5-V keyed PCI segment with an RJ-45 Ethernet connector - Integrated on-board Intel® EtherExpress...
... the JEDEC PC133 specification - CNB30LE North Bridge - Four DIMM slots allow a maxiumum installed memory of both primary and secondary processors • ServerWorks* ServerSet* III LE chipset - 133-MHz Front Side Bus (FSB) Capability - SAI2 Server Board TPS Introduction 1. Two 64-bit, 66-MHz..., 3.3-V keyed PCI expansion slots • 32-bit, 33-MHz, 5-V keyed PCI segment with an RJ-45 Ethernet connector - Integrated on-board Intel® EtherExpress...
Product Specification
Page 15
...The CSB5 South Bridge provides a number of DIMMS, Intel recommends that module and DRAM vendors not be used....Intel Pentium III processor. Revision 1.0 5 The CNB30LE North Bridge is both the 64-bit, 66-MHz, Revision 2.2-compliant PCI bus and the 32-bit, 33-MHz, Revision 2.2-compliant PCI bus. The SAI2...SAI2 server board contains four 168-pin DIMM sockets. SAI2 Server Board TPS SAI2 Server Board Architecture Overview 2.2 ServerWorks ServerSet III LE Chipset The ServerWorks ServerSet III LE... the SAI2 server board architecture allows the user to one of single interleaved memory (64-bit ...
...The CSB5 South Bridge provides a number of DIMMS, Intel recommends that module and DRAM vendors not be used....Intel Pentium III processor. Revision 1.0 5 The CNB30LE North Bridge is both the 64-bit, 66-MHz, Revision 2.2-compliant PCI bus and the 32-bit, 33-MHz, Revision 2.2-compliant PCI bus. The SAI2...SAI2 server board contains four 168-pin DIMM sockets. SAI2 Server Board TPS SAI2 Server Board Architecture Overview 2.2 ServerWorks ServerSet III LE Chipset The ServerWorks ServerSet III LE... the SAI2 server board architecture allows the user to one of single interleaved memory (64-bit ...
Product Specification
Page 16
... SAI2 server board meet the needs of one 64-bit / 66-MHz bus segment and one 32-bit / 33-MHz bus segment. Each of the PCI buses comply with Revision 2.2 of the PCI Local Bus Specification. 2.4.1 64-bit / 66 MHz PCI Subsystem The 64-...64-bit data transfers • Plug-and-Play ready • Parity enabled 2.4.2 32-bit/33 MHz PCI Subsystem The 32-bit, 33-MHz, 5-V keyed PCI includes the following embedded devices and connectors: • Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots • Integrated Intel® EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller (Intel...
... SAI2 server board meet the needs of one 64-bit / 66-MHz bus segment and one 32-bit / 33-MHz bus segment. Each of the PCI buses comply with Revision 2.2 of the PCI Local Bus Specification. 2.4.1 64-bit / 66 MHz PCI Subsystem The 64-...64-bit data transfers • Plug-and-Play ready • Parity enabled 2.4.2 32-bit/33 MHz PCI Subsystem The 32-bit, 33-MHz, 5-V keyed PCI includes the following embedded devices and connectors: • Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots • Integrated Intel® EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller (Intel...
Product Specification
Page 18
...receive interrupt for concurrent processing of 32-bit PCI signals because it never acts as a PCI master. The SAI2 supports the following features of the 82559 controller: • Glueless 32-bit PCI Bus Master Interface (Direct Drive of Bus), compatible with PCI Bus Specification, revision 2.1 / 2.2 &#... monitors, single- The Rage XL, 64-bit VGA Graphics Accelerator contains a SVGA video controller, clock generator, BitBLT engine, and RAMDAC. A flash device stores the network ID. • Support for Wake-on-LAN (WOL) 2.4.2.2 Video Controller The SAI2 server board includes an ATI Rage XL...
...receive interrupt for concurrent processing of 32-bit PCI signals because it never acts as a PCI master. The SAI2 supports the following features of the 82559 controller: • Glueless 32-bit PCI Bus Master Interface (Direct Drive of Bus), compatible with PCI Bus Specification, revision 2.1 / 2.2 &#... monitors, single- The Rage XL, 64-bit VGA Graphics Accelerator contains a SVGA video controller, clock generator, BitBLT engine, and RAMDAC. A flash device stores the network ID. • Support for Wake-on-LAN (WOL) 2.4.2.2 Video Controller The SAI2 server board includes an ATI Rage XL...
Product Specification
Page 21
...SAI2 server board provides a dual external USB connector interface. Revision 1.0 11 Both ports function identically and with Revision 2.2 of CSB5 South Bridge is used to distribute 16 PCI interrupts. The USB controller moves data between main memory and the two USB connectors provided. The SAI2...Interface The CSB5 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for an internally mounted CD-ROM. The IDE ...board. SAI2 supports sleep states s0, s1, s4, and s5. The external connector is defined by Revision 1.0 of the USB Specification. 2.4.2.4...
...SAI2 server board provides a dual external USB connector interface. Revision 1.0 11 Both ports function identically and with Revision 2.2 of CSB5 South Bridge is used to distribute 16 PCI interrupts. The USB controller moves data between main memory and the two USB connectors provided. The SAI2...Interface The CSB5 South Bridge acts as a PCI-based enhanced IDE 32-bit interface controller for an internally mounted CD-ROM. The IDE ...board. SAI2 supports sleep states s0, s1, s4, and s5. The external connector is defined by Revision 1.0 of the USB Specification. 2.4.2.4...
Product Specification
Page 28
... system and the OS policy determines the entry methods and wake up event capabilities are provided by the hardware but are still running. The SAI2 server board supports sleep states s0, s1, s4, and s5. If the system power is set is running in ACPI mode, the ...When the server board is operating in this state the power supply is still on remotely by sending a specific packet from the disk and resumes normal operation. SAI2 Server Board Architecture Overview SAI2 Server Board TPS 2.7 ACPI The Advance Configuration and Power Interface (ACPI)-aware operating system can changed by ...
... system and the OS policy determines the entry methods and wake up event capabilities are provided by the hardware but are still running. The SAI2 server board supports sleep states s0, s1, s4, and s5. If the system power is set is running in ACPI mode, the ...When the server board is operating in this state the power supply is still on remotely by sending a specific packet from the disk and resumes normal operation. SAI2 Server Board Architecture Overview SAI2 Server Board TPS 2.7 ACPI The Advance Configuration and Power Interface (ACPI)-aware operating system can changed by ...
Product Specification
Page 29
... system functionality using stored configuration values. Phoenix* Phlash (PHLASH.EXE) is the break-down of the SAI2 product ID string: • 4-byte board ID, 'SAI2' • 1-byte board revision, starting from the peripheral device manufacturers and loaded into the baseboard flash... option ROMs for these adapters; The BIOS contains standard PC-compatible basic input/output (I/O) services, standard Intel® server features, plus the SAI2 system-specific hardware configuration routines and register default settings, embedded in hhmm format Revision 1.0 19 The BIOS is not...
... system functionality using stored configuration values. Phoenix* Phlash (PHLASH.EXE) is the break-down of the SAI2 product ID string: • 4-byte board ID, 'SAI2' • 1-byte board revision, starting from the peripheral device manufacturers and loaded into the baseboard flash... option ROMs for these adapters; The BIOS contains standard PC-compatible basic input/output (I/O) services, standard Intel® server features, plus the SAI2 system-specific hardware configuration routines and register default settings, embedded in hhmm format Revision 1.0 19 The BIOS is not...
Product Specification
Page 30
...; Intel Multi-Processor Specification (MPS) support • Server management and error handling • CMOS configuration RAM management • OEM customization • PCI and Plug and Play (PnP) BIOS interface • Console redirection • Resource allocation support BIOS setup is provided. On the SAI2 platform... advanced programmable interrupts (APIs) to change , as SCSI, NIC, and video controllers. A 64-KB parameter block in the flash ROM is read by Intel. In addition, the system BIOS supports certain features that controls extended system configuration data (ESCD),...
...; Intel Multi-Processor Specification (MPS) support • Server management and error handling • CMOS configuration RAM management • OEM customization • PCI and Plug and Play (PnP) BIOS interface • Console redirection • Resource allocation support BIOS setup is provided. On the SAI2 platform... advanced programmable interrupts (APIs) to change , as SCSI, NIC, and video controllers. A 64-KB parameter block in the flash ROM is read by Intel. In addition, the system BIOS supports certain features that controls extended system configuration data (ESCD),...
Product Specification
Page 31
SAI2 Server Board TPS Basic Input Output System (BIOS) 3.2 Setup Utility This section describes ... If data is divided into submenus. Setup Utility Screen Functional Area Keyboard Command Bar Menu Selection Bar Options Menu Item Specific Help Screen Description Located at the bottom of the screen. Setup provides sufficient configuration functionality to enter Setup Revision 1.0... you into four functional areas. Located at the top of the screen is an item-specific Help screen. 3.2.2.1 Entering Setup Utility During POST operation, the user is detectable by the setup utility.
SAI2 Server Board TPS Basic Input Output System (BIOS) 3.2 Setup Utility This section describes ... If data is divided into submenus. Setup Utility Screen Functional Area Keyboard Command Bar Menu Selection Bar Options Menu Item Specific Help Screen Description Located at the bottom of the screen. Setup provides sufficient configuration functionality to enter Setup Revision 1.0... you into four functional areas. Located at the top of the screen is an item-specific Help screen. 3.2.2.1 Entering Setup Utility During POST operation, the user is detectable by the setup utility.
Product Specification
Page 42
... by CMOS clear. If the switch is cleared via jumper. Basic Input Output System (BIOS) SAI2 Server Board TPS Table 23. Write all Setup items from floppy. The CMOS map is subject ...If the Reset Configuration Data option is enabled in Setup, ESCD data and BIOS Boot specification data is cleared and reinitialized in which each removable device is available in the NVRAM... Devices Selections Boot Priority Device 1 Legacy Floppy Drives Description Select the order in next boot. 32 Revision 1.0 Password settings are available on or a hard reset, the BIOS changes the CMOS and...
... by CMOS clear. If the switch is cleared via jumper. Basic Input Output System (BIOS) SAI2 Server Board TPS Table 23. Write all Setup items from floppy. The CMOS map is subject ...If the Reset Configuration Data option is enabled in Setup, ESCD data and BIOS Boot specification data is cleared and reinitialized in which each removable device is available in the NVRAM... Devices Selections Boot Priority Device 1 Legacy Floppy Drives Description Select the order in next boot. 32 Revision 1.0 Password settings are available on or a hard reset, the BIOS changes the CMOS and...
Product Specification
Page 44
Dealers can be placed in this user binary. Intel provides tools and reference code to this section. The user ...of the system BIOS. The checksum byte must adhere to store a user binary. User binary can manage dealer-specific hardware, if any, by executing their own code during POST. If the user binary reports that the user...is passed to help dealers create a user binary. At several points throughout POST, control is updated. 3.5.2 Customization The SAI2 BIOS can change the BIOS look and feel. Mask bits must have an option ROM header (i.e., 55AAh, size). &#...
Dealers can be placed in this user binary. Intel provides tools and reference code to this section. The user ...of the system BIOS. The checksum byte must adhere to store a user binary. User binary can manage dealer-specific hardware, if any, by executing their own code during POST. If the user binary reports that the user...is passed to help dealers create a user binary. At several points throughout POST, control is updated. 3.5.2 Customization The SAI2 BIOS can change the BIOS look and feel. Mask bits must have an option ROM header (i.e., 55AAh, size). &#...
Product Specification
Page 69
... TPS Baseboard Specifications 6. Baseboard Specifications This chapter specifies the operational parameters and physical characteristics for SAI2/SC5100 Sub Assembly Description Baseboard Front panel board (typ) Processor Hard Drive PRO 100 B IDE CD-ROM (typ) Power supply (typ) 1.44MB 3.5" FDU (typ) 32 Meg DIMM (typ)...2,469 3,533 10,410 38,004 26,313 Revision 1.0 59 This is a board-level specification only. Estimated MTBF Calculated Numbers for the SAI2 server board. System specifications are beyond the scope of this document. 6.1 Estimated Baseboard MTBF The table below shows the...
... TPS Baseboard Specifications 6. Baseboard Specifications This chapter specifies the operational parameters and physical characteristics for SAI2/SC5100 Sub Assembly Description Baseboard Front panel board (typ) Processor Hard Drive PRO 100 B IDE CD-ROM (typ) Power supply (typ) 1.44MB 3.5" FDU (typ) 32 Meg DIMM (typ)...2,469 3,533 10,410 38,004 26,313 Revision 1.0 59 This is a board-level specification only. Estimated MTBF Calculated Numbers for the SAI2 server board. System specifications are beyond the scope of this document. 6.1 Estimated Baseboard MTBF The table below shows the...
Product Specification
Page 70
...cause permanent damage to the appropriate system chassis document for the SAI2 server board. Refer to the system (provided for stress testing only). Baseboard Specifications SAI2 Server Board TPS 6.2 Absolute Maximum Ratings Operation of the ...V 5-V Standby 0.1 0.1 0.5 0.2 0.1 Total 60 Revision 1.0 SAI2 Server Board Calculated Power Consumption Device(s) 3.3 V Server Board 2.5 2.5 Processors 15 Memory (Four PC133 5.6 Registered GB SDRAM DIMMs) PCI Connectors 6.1 8.0 32-bit PCI slots (10 W per slot on 5 V) 64-bit PCI slots (10 W per slot on any signal with ...
...cause permanent damage to the appropriate system chassis document for the SAI2 server board. Refer to the system (provided for stress testing only). Baseboard Specifications SAI2 Server Board TPS 6.2 Absolute Maximum Ratings Operation of the ...V 5-V Standby 0.1 0.1 0.5 0.2 0.1 Total 60 Revision 1.0 SAI2 Server Board Calculated Power Consumption Device(s) 3.3 V Server Board 2.5 2.5 Processors 15 Memory (Four PC133 5.6 Registered GB SDRAM DIMMs) PCI Connectors 6.1 8.0 32-bit PCI slots (10 W per slot on 5 V) 64-bit PCI slots (10 W per slot on any signal with ...
Product Specification
Page 71
... is listed in the following table. SAI2 Server Board TPS Device(s) 3.3 V Fans (Four chassis and two processor) Total Current 14.2 27 Total Power 46.86 135 +5 V Baseboard Specifications +12 V 1.94 -12 V 5-V Standby Total 2.24 0.2 0.5 26.88 2.4 2.5 43.48 213.64 The total power calculation assumes a system configuration containing dual Pentium® III 1.26GHz processors...
... is listed in the following table. SAI2 Server Board TPS Device(s) 3.3 V Fans (Four chassis and two processor) Total Current 14.2 27 Total Power 46.86 135 +5 V Baseboard Specifications +12 V 1.94 -12 V 5-V Standby Total 2.24 0.2 0.5 26.88 2.4 2.5 43.48 213.64 The total power calculation assumes a system configuration containing dual Pentium® III 1.26GHz processors...
Product Specification
Page 77
SAI2 Server Board...IRQ ISA LAN LED LSB LUN LVD MP MPS MSB MTBF NIC NMI NRTL NVRAM Definition Advanced Configuration and Power Interface Advanced Programmable Interrupt Intel Advanced ...Programmable Interrupt Controller Binary Data Area Basic Input Output System Complementary Metal-Oxide Semi-Conductor Dual In-Line Memory ...Emitting Diode Least Significant Bit Logical Unit Number Low Voltage Differential Multiprocessor Intel Multi-Processor Specification Most Significant Bit Mean Time Between Failures Network Interface Card Non-Maskable ...
SAI2 Server Board...IRQ ISA LAN LED LSB LUN LVD MP MPS MSB MTBF NIC NMI NRTL NVRAM Definition Advanced Configuration and Power Interface Advanced Programmable Interrupt Intel Advanced ...Programmable Interrupt Controller Binary Data Area Basic Input Output System Complementary Metal-Oxide Semi-Conductor Dual In-Line Memory ...Emitting Diode Least Significant Bit Logical Unit Number Low Voltage Differential Multiprocessor Intel Multi-Processor Specification Most Significant Bit Mean Time Between Failures Network Interface Card Non-Maskable ...
Product Specification
Page 79
... XL Technical Reference Manual. • I2C Bus Specification. • Intel 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet. • PCI Local Bus Specification, Revision 2.2. • ServerWorks ServerSet* III LE North Bridge Specification. • ServerWorks ServerSet* III LE South Bridge Specification. • USB Specification, Revision 1.0. • VRM 8.4 DC-DC Converter Specification. • Wired For Management Baseline Specification, Revision 2.0 Revision 1.0 III
... XL Technical Reference Manual. • I2C Bus Specification. • Intel 82559 Fast Ethernet Multifunction PCI/CardBus Controller Datasheet. • PCI Local Bus Specification, Revision 2.2. • ServerWorks ServerSet* III LE North Bridge Specification. • ServerWorks ServerSet* III LE South Bridge Specification. • USB Specification, Revision 1.0. • VRM 8.4 DC-DC Converter Specification. • Wired For Management Baseline Specification, Revision 2.0 Revision 1.0 III
Product Specification
Page 81
SAI2 Server Board TPS Front Panel reset, 32 Front Side Bus, 1 H HDD LED pinout, 50 Hipower* test suite, 61 I I2C connector pinout, 49 ICH, 7 IDE connector pinout, 53 IDE controller, 5, 6 IDE Controller, 28 Intel® 82559, 1, 6, 7, 8, 17 Intel® Celeron™ processor, 3 Intel® EtherExpress™ ...9 Mouse connector, 46 Revision 1.0 MPS, 20, 25 MTBF, 59, I Multi-Processor Specification, 20 N Network connector, 46 NMI switch, 46 North Bridge, 1, 5, 17 NVRAM, 21, 32 NVRAM.LST, 32 P Parallel port connector, 46 Parallel port connector pinout, 52 Password Change, 47 Disable jumper...
SAI2 Server Board TPS Front Panel reset, 32 Front Side Bus, 1 H HDD LED pinout, 50 Hipower* test suite, 61 I I2C connector pinout, 49 ICH, 7 IDE connector pinout, 53 IDE controller, 5, 6 IDE Controller, 28 Intel® 82559, 1, 6, 7, 8, 17 Intel® Celeron™ processor, 3 Intel® EtherExpress™ ...9 Mouse connector, 46 Revision 1.0 MPS, 20, 25 MTBF, 59, I Multi-Processor Specification, 20 N Network connector, 46 NMI switch, 46 North Bridge, 1, 5, 17 NVRAM, 21, 32 NVRAM.LST, 32 P Parallel port connector, 46 Parallel port connector pinout, 52 Password Change, 47 Disable jumper...
