Product Specification
Page 34
...connection between the processor and C202 chipset. The external graphics ports support 5.0 GT/s speed as defined in each direction, which provides a 250-MB/s communications channel in the PCI Plug-andPlay specification. The PCI Express* architecture is specified in the component is not necessarily along these same ...Physical Layer. One PCI-E x8 connector to be used as x4 link connected to the PCE ports of PCH. Intel® Server Board S1200BTS One PCI-E x16 connector to six ports and supports data transfer rates of the processor. The initial recovered clock speed of the...
...connection between the processor and C202 chipset. The external graphics ports support 5.0 GT/s speed as defined in each direction, which provides a 250-MB/s communications channel in the PCI Plug-andPlay specification. The PCI Express* architecture is specified in the component is not necessarily along these same ...Physical Layer. One PCI-E x8 connector to be used as x4 link connected to the PCE ports of PCH. Intel® Server Board S1200BTS One PCI-E x16 connector to six ports and supports data transfer rates of the processor. The initial recovered clock speed of the...
Product Specification
Page 40
...Supported 32bpp Supported Supported Supported Supported Supported Supported 3.7.1.2 Dual Video The BIOS supports both CRT and LCD. Functional Architecture Intel®Server Board S1200BT TPS 3.6.5 Keyboard and Mouse Support The server board does not support PS/2 interface keyboards and mouse. Attached memory...In the single mode (dual monitor video = disabled), the on -board Server Engine* LLC Pilot III* Controller with 128 MB DDR3 memory in video card is usable/accessible memory for display functions. 3.7.1.1 Video Modes The integrated video controller supports all standard IBM...
...Supported 32bpp Supported Supported Supported Supported Supported Supported 3.7.1.2 Dual Video The BIOS supports both CRT and LCD. Functional Architecture Intel®Server Board S1200BT TPS 3.6.5 Keyboard and Mouse Support The server board does not support PS/2 interface keyboards and mouse. Attached memory...In the single mode (dual monitor video = disabled), the on -board Server Engine* LLC Pilot III* Controller with 128 MB DDR3 memory in video card is usable/accessible memory for display functions. 3.7.1.1 Video Modes The integrated video controller supports all standard IBM...
Product Specification
Page 41
...Transceiver (PHY). the other is a video chip from the onboard Intel® 82574L GbE PCI Express network controller; The 82579 supports operation at 1000/100/10 Mb/s data rates. Intel®Server Board S1200BT TPS Functional Architecture In dual mode, the onboard video...33 MHz & 66 MHz PCI Master/Slave interface PCI 2.1 compliant Memory control is provided for Intel® Server Board S1200BTS SM712 is the onboard Intel® 82579 Gigabit Network controller. 3.8.1 Gigabit Ethernet Controller 82574L The 82574 family (82574L and 82574IT) are enabled for...
...Transceiver (PHY). the other is a video chip from the onboard Intel® 82574L GbE PCI Express network controller; The 82579 supports operation at 1000/100/10 Mb/s data rates. Intel®Server Board S1200BT TPS Functional Architecture In dual mode, the onboard video...33 MHz & 66 MHz PCI Master/Slave interface PCI 2.1 compliant Memory control is provided for Intel® Server Board S1200BTS SM712 is the onboard Intel® 82579 Gigabit Network controller. 3.8.1 Gigabit Ethernet Controller 82574L The 82574 family (82574L and 82574IT) are enabled for...
Product Specification
Page 42
... to 10 Mb/s (dependent on Intel® Architecture Processors. The PCIe interface incorporates two aspects: a PCIe SerDes (electrically) and a custom logic protocol. 3.8.3 MAC Address Definition Each Intel® Server Board S1200BTL has the following two MAC addresses assigned to it at the Intel® factory... NIC 1 MAC address NIC 2 MAC address - Assigned the NIC 1 MAC address +3 Each Intel® Server Board S1200BTS has the following four MAC addresses assigned to it at the Intel® factory: NIC 1 MAC address NIC 2 MAC address - Note: If the ...
... to 10 Mb/s (dependent on Intel® Architecture Processors. The PCIe interface incorporates two aspects: a PCIe SerDes (electrically) and a custom logic protocol. 3.8.3 MAC Address Definition Each Intel® Server Board S1200BTL has the following two MAC addresses assigned to it at the Intel® factory... NIC 1 MAC address NIC 2 MAC address - Assigned the NIC 1 MAC address +3 Each Intel® Server Board S1200BTS has the following four MAC addresses assigned to it at the Intel® factory: NIC 1 MAC address NIC 2 MAC address - Note: If the ...
Product Specification
Page 69
... Text: Comments: Information only. Displays the Platform ID for this BIOS 4. Logged in : Administrator or User. BIOS Version Option Values: Help Text: Comments: Information only. Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Build Date Option Values: (built)>
... Text: Comments: Information only. Displays the Platform ID for this BIOS 4. Logged in : Administrator or User. BIOS Version Option Values: Help Text: Comments: Information only. Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Build Date Option Values: (built)>
Product Specification
Page 75
Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Microcode Revision Option Values: Help Text:... two types of L1 cache for the SandyBridge processor family, this is not shared between all cores in MB of L2 cache per processor package. Since L2 cache is shown as the amount of L1 Instruction Cache ... cores, this is shown as the total amount of the currently loaded processor microcode. 3. S1200BT boards have ―N/A‖ for each core. 4. Displays Revision Level of L3 cache per core. 5. Processor Version Revision 1.0...
Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Microcode Revision Option Values: Help Text:... two types of L1 cache for the SandyBridge processor family, this is not shared between all cores in MB of L2 cache per processor package. Since L2 cache is shown as the amount of L1 Instruction Cache ... cores, this is shown as the total amount of the currently loaded processor microcode. 3. S1200BT boards have ―N/A‖ for each core. 4. Displays Revision Level of L3 cache per core. 5. Processor Version Revision 1.0...
Product Specification
Page 81
Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Displays the amount of memory available in the system in the form of installed DDR3 DIMMs, in units of all DDR3 DIMMs that failed Memory BIST during POST or were disabled by the BIOS during the memory discovery phase in MB... or GB. Revision 1.0 69 Intel order number G13326-003 Effective Memory Option Values: Help Text: Comments: OS in order to the The Effective Memory...
Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Displays the amount of memory available in the system in the form of installed DDR3 DIMMs, in units of all DDR3 DIMMs that failed Memory BIST during POST or were disabled by the BIOS during the memory discovery phase in MB... or GB. Revision 1.0 69 Intel order number G13326-003 Effective Memory Option Values: Help Text: Comments: OS in order to the The Effective Memory...
Product Specification
Page 149
...ARP ASIC ASMI BIOS BIST BMC Bridge BSP Byte CBC CEK CHAP CMOS DHCP DPC EEPROM EHCI EMP EPS ESB2 FBD F MB FRB FRU FSB GB GPA GPIO GTL HPA HSC Definition Advanced Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Address ...Fault Resilient Booting Field Replaceable Unit Front Side Bus 1024 MB Guest Physical Address General Purpose I/O Gunning Transceiver Logic Host Physical Address Hot-swap Controller Revision 1.0 137 Intel order number G13326-003 Intel®Server Board S1200BT TPS Glossary Glossary This appendix contains important terms used in...
...ARP ASIC ASMI BIOS BIST BMC Bridge BSP Byte CBC CEK CHAP CMOS DHCP DPC EEPROM EHCI EMP EPS ESB2 FBD F MB FRB FRU FSB GB GPA GPIO GTL HPA HSC Definition Advanced Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Address ...Fault Resilient Booting Field Replaceable Unit Front Side Bus 1024 MB Guest Physical Address General Purpose I/O Gunning Transceiver Logic Host Physical Address Hot-swap Controller Revision 1.0 137 Intel order number G13326-003 Intel®Server Board S1200BT TPS Glossary Glossary This appendix contains important terms used in...
Product Specification
Page 150
... Register Multiplexor Network Interface Controller Non-maskable Interrupt Output Buffer Original Equipment Manufacturer Unit of electrical resistance Over-voltage Protection Intel order number G13326-003 Intel®Server Board S1200BT TPS Revision 1.0 Hashing Algorithm Message Digest 5 - Glossary Term Hz I2C IA IBF ICH ICMB IERR IFB ILM ...IMC INTR I/OAT IOH IP IPMB IPMI IR ITP KB KCS KVM LAN LCD LDAP LED LPC LUN MAC MB MCH MD2 MD5...
... Register Multiplexor Network Interface Controller Non-maskable Interrupt Output Buffer Original Equipment Manufacturer Unit of electrical resistance Over-voltage Protection Intel order number G13326-003 Intel®Server Board S1200BT TPS Revision 1.0 Hashing Algorithm Message Digest 5 - Glossary Term Hz I2C IA IBF ICH ICMB IERR IFB ILM ...IMC INTR I/OAT IOH IP IPMB IPMI IR ITP KB KCS KVM LAN LCD LDAP LED LPC LUN MAC MB MCH MD2 MD5...