Data Sheet
Page 69
...priority agent asserts BPRI# to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of the first transaction to the system that a...processor has reached its maximum safe operating temperature. The TCC will activate the TCC, if enabled. PSI# can be used to Vss. See Chapter 5.3 for more details. As an alternative to MSID, Intel...those names on an interposer. Refer to Section 2.5 for a debug port implemented on the Pentium processor. Input/ PECI is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal,...
...priority agent asserts BPRI# to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of the first transaction to the system that a...processor has reached its maximum safe operating temperature. The TCC will activate the TCC, if enabled. PSI# can be used to Vss. See Chapter 5.3 for more details. As an alternative to MSID, Intel...those names on an interposer. Refer to Section 2.5 for a debug port implemented on the Pentium processor. Input/ PECI is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal,...