Specifications
Page 91
...tZAD tZFS DSTROBE (device) tAZ tDZFS tDVS tDVH D D (15 :0 ) tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for output drivers turning on tENV tZIORDY 20 70 20 70 20 70 20 55 20 55 20 50 Envelope time 0 0 0 0 0 0 Minimum time waiting before ...from data output released- to-driving until the first transition of critical timing tACK 20 20 20 20 20 20 Setup and hold time at sender tFS 230 200 170 130 120 90 First strobe tUI 0 0 0 0 0 0 Unlimited interlock tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAD 0 0 ...
...tZAD tZFS DSTROBE (device) tAZ tDZFS tDVS tDVH D D (15 :0 ) tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for output drivers turning on tENV tZIORDY 20 70 20 70 20 70 20 55 20 55 20 50 Envelope time 0 0 0 0 0 0 Minimum time waiting before ...from data output released- to-driving until the first transition of critical timing tACK 20 20 20 20 20 20 Setup and hold time at sender tFS 230 200 170 130 120 90 First strobe tUI 0 0 0 0 0 0 Unlimited interlock tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAD 0 0 ...
Specifications
Page 94
...tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for the STOP, HDMARDY and DSTROBE signal lines are no longer... in effect after DMARQ and DMACK are negated. Note: The definitions for output drivers turning on tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times...
...tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for the STOP, HDMARDY and DSTROBE signal lines are no longer... in effect after DMARQ and DMACK are negated. Note: The definitions for output drivers turning on tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times...
Specifications
Page 95
... tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for the STOP, HDMARDY and DSTROBE signal lines are no longer... in effect after DMARQ and DMACK are negated. Note: The definitions for output drivers turning on tRFS 75 70 60 60 60 50 Ready-to-final-STROBE time tRP 160 125 100 100 100 85 Ready-to-pause time...
... tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tZAH 20 20 20 20 20 20 Minimum delay time for the STOP, HDMARDY and DSTROBE signal lines are no longer... in effect after DMARQ and DMACK are negated. Note: The definitions for output drivers turning on tRFS 75 70 60 60 60 50 Ready-to-final-STROBE time tRP 160 125 100 100 100 85 Ready-to-pause time...
Specifications
Page 99
...) Mode5(ns) Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6.7 10 CRC word valid setup time at sender tCVH 6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold times for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and... time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to negation of DMARQ or assertion of STOP K6602637 Rev.3 02.27.01 - 99 -
...) Mode5(ns) Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6.7 10 CRC word valid setup time at sender tCVH 6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold times for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and... time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to negation of DMARQ or assertion of STOP K6602637 Rev.3 02.27.01 - 99 -