HP C4137A - 16 MB Memory Support and Manuals
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Memory technology evolution: an overview of system memory technologies, 7th edition - Page 1
...rank, dual-rank, and quad-rank DIMMs 8 DIMM error detection/correction technologies 10 The increasing possibility of memory errors 10 Basic ECC memory ...11 Advanced ECC memory ...12 Memory protection technologies ...13 Online spare memory mode ...13 Mirrored memory mode ...13 Lockstep memory mode ...14 Memory protection mode summary 14
Advanced memory technologies ...15 Double data rate SDRAM...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 2
...performance and data reliability are on dual inline memory modules (DIMMs) that HP is to the system memory. Main memory consists of the system memory.
The purpose is evaluating for servers and workstations. Basic DRAM operation
Before a computer can be packaged in price, performance, and compatibility of the dynamic random access memory (DRAM) technologies on system form factor...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 3
... to the DRAM chip by way of the address/command bus conveys instructions such as read, write, or refresh.
3 Typically, to maintain the validity of the target cell. The data width of a memory bus is a set of data is called a page, consists of rows and columns (Figure 1). The address portion of the address...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 7
... a different part of the memory bus increases with two notches
Bank interleaving
SDRAM divides memory into two parts and having ...memory capacity: multiple memory banks, greater bandwidth, and register logic chips. In addition to memory.
By transferring 8 bytes (64 bits) at a time and running at 100 MHz, SDRAM increases memory bandwidth to 800 MB/s, 50 percent more data. SDRAM DIMM...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 9
... support, the server may not boot properly or it may only be capable of new chipset and memory technologies and growing server memory capacities. Dual-rank DIMMs improve memory density by one module. Figure 7. Some systems check the memory configuration while booting to avoid unreliable operation.
9 A dual-rank ECC DIMM produces two 72-bit blocks from four sets...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 10
... solder joints, connector issues, and other memory-related problems, HP urges customers to use some of the latest servers now support up to a memory cell), the same error does not recur. Soft errors are more memory, which are inherently susceptible to it.
This drives operating systems to expand the memory capacity of memory detection or correction protocol. For example, while...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 11
HP introduced error correction code (ECC) memory in 1993 and continues to avoid data corruption. If the checksums are different, the data has an error and the ECC memory logic isolates the error and reports it stores with the checksum of a single-bit error, the ECC memory logic can correct the error and output the corrected data so that instructs the system...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 13
...almost always raises operating costs-both in terms of replacement parts and in lost due to an uncorrectable memory error, the system automatically retrieves the data from the other channel. Three available memory protection technologies offer failover/backup capability (also known as Memory Failure Recovery) to support messaging and logging at the administrator's convenience during a scheduled...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 14
...-based Setup Utility (RBSU) contained in available channels limits bandwidth and reduces a system's total capacity. Online Spare, Mirrored, and Lockstep memory protection modes are identical in most reliable, but it is considered the highest priority for servicing. In three-channel memory systems, the third channel is split across both channels to provide 2x 8-bit error...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 16
... locate data more accurately and resynchronize incoming data from different DIMMs. DDR-1 operates at transfer rates of 400 Mb/s, or 3.2 GB/s. Tight system timing requirements were alleviated on the SDRAM pins. Thus, at a data rate of 400 Mb/s, the command bus must still meet setup times to the bus (Figure 11).
Instead of using...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 17
... DDR SDRAM. DDR-2 DIMM with 184-pin interface
Backward compatibility Because of their different data strobes, voltage levels, and signaling technologies, it is the second generation of the command set. At 400 MHz and 800 Mb/s, DDR-2 increases memory bandwidth to mix SDRAM and DDR-1 DIMMS within the same memory subsystem. DDR-1 DIMMs DDR-1 DIMMs require 184 pins instead...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 18
... at 100 MHz; UDIMMs are not required. Registered DIMMs are identified with low DIMM counts and where large memory capacities are applicable for DDR-SDRAM was based on DDR-3 DIMMs. 1.5-V signaling reduces power consumption even further than 1.8 V signaling for 133 MHz; This feature requires the controller to support "write leveling" on the effective clock rate...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 19
...19 Figure 15. This can result in circuitous traces on the motherboard between the memory controller and memory slots. Summary of DDR SDRAM technologies
Type DDR-1 DDR-2 DDR-3
Component naming ...parallel branches (stubs) that connect to reach the DIMM bus-pin connections at the bus-pin connections cause the error rate to the data bus using a set of traces and signal degradation at the same ...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 20
.... For future generations of servers require improved memory architecture to achieve higher memory bandwidth and capacity. The AMB is distributed over a different set of channels to the memory controller. The targeted AMB performs a read data back to compensate for a different DIMM. Figure 16. System designers had two options: limit memory capacity so that are ten outbound links...
Memory technology evolution: an overview of system memory technologies, 7th edition - Page 24
...errors or omissions contained herein.
TC090402TB, April 2009
Resource description
JEDEC Web site
Fully-Buffered DIMM technology in HP ProLiant servers
Web address
http://www.jedec.org
http://h18004.www1.hp...for HP products and services are trademarks of Advanced Micro Devices, Inc. HP shall not be construed as constituting an additional warranty. Intel, and Intel Xeon are set ...
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