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... as two 32-byte cache lines. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 System Bus Interface Unit 32-Kbyte L1 Instruction Cache Tag Way 0 State Tag Way 1 State RAM Bit RAM Bit 64-Entry TLB Pre-Decode Instruction Cache 128...Tag MESI Tag MESI RAM Way 0 Bits RAM Way 1 Bits RAM Way 2 Bits RAM Way 3 Bits 128-Kbyte L2 Cache Figure 82. Each sector consists of each cache line. 206 Cache Organization Chapter 9 L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor The processor cache design takes advantage...
... as two 32-byte cache lines. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 System Bus Interface Unit 32-Kbyte L1 Instruction Cache Tag Way 0 State Tag Way 1 State RAM Bit RAM Bit 64-Entry TLB Pre-Decode Instruction Cache 128...Tag MESI Tag MESI RAM Way 0 Bits RAM Way 1 Bits RAM Way 2 Bits RAM Way 3 Bits 128-Kbyte L2 Cache Figure 82. Each sector consists of each cache line. 206 Cache Organization Chapter 9 L1 and L2 Cache Organization for the AMD-K6™-2E+ Processor The processor cache design takes advantage...
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...RAM. The default code-segment (CS) base address for the SMM service routine is at 0003_0000h. is 0003_8000h. SMM Memory 0003_0000h 242 System Management Mode (SMM) Chapter 12 The default entry point for the area-called the SMM base address - Preliminary Information AMD-K6™-2E+ Embedded Processor... (0003_8000h to 0003_FFFFh) contain a fill-down SMM state-save area. Fill Down SMM State-Save Area 0003_FFFFh 0003_FE00h 32-Kbyte Minimum RAM Service Routine Entry Point SMM Service Routine 0003_8000h SMM Base Address (CS) Figure 89. It con sists of a 64 -Kbyte area...
...RAM. The default code-segment (CS) base address for the SMM service routine is at 0003_0000h. is 0003_8000h. SMM Memory 0003_0000h 242 System Management Mode (SMM) Chapter 12 The default entry point for the area-called the SMM base address - Preliminary Information AMD-K6™-2E+ Embedded Processor... (0003_8000h to 0003_FFFFh) contain a fill-down SMM state-save area. Fill Down SMM State-Save Area 0003_FFFFh 0003_FE00h 32-Kbyte Minimum RAM Service Routine Entry Point SMM Service Routine 0003_8000h SMM Base Address (CS) Figure 89. It con sists of a 64 -Kbyte area...
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...Lookaside Buffers (TLBs) Chapter 13 Test and Debug 251 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 13 13.1 Test and Debug The AMD-K6-2E+ processor implements various test and debug modes to enable the functional and manufacturing testing of systems... and boards that exercise most on-chip RAM structures. s Level-2 Cache Array Access Register (L2AAR)-The AMD-K6-2E+ processor provides the L2AAR that ...
...Lookaside Buffers (TLBs) Chapter 13 Test and Debug 251 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 13 13.1 Test and Debug The AMD-K6-2E+ processor implements various test and debug modes to enable the functional and manufacturing testing of systems... and boards that exercise most on-chip RAM structures. s Level-2 Cache Array Access Register (L2AAR)-The AMD-K6-2E+ processor provides the L2AAR that ...