User Guide
Page 202
...AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 AHOLD Restriction When the system logic drives an AHOLD-initiated inquire cycle, it must assert AHOLD for the pending write cycle) and the address bus off the same clock edge that switches the address bus (A[31:3] and AP), the processor switches 102 drivers... a write cycle is pipelined into a read cycle is sampled asserted to ground-bounce spikes. The processor's 32 address bus drivers turn on page 181). If the processor switches the data bus (D[63:0] and DP[7:0]) during a writeback cycle, it must ensure that AHOLD...
...AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 AHOLD Restriction When the system logic drives an AHOLD-initiated inquire cycle, it must assert AHOLD for the pending write cycle) and the address bus off the same clock edge that switches the address bus (A[31:3] and AP), the processor switches 102 drivers... a write cycle is pipelined into a read cycle is sampled asserted to ground-bounce spikes. The processor's 32 address bus drivers turn on page 181). If the processor switches the data bus (D[63:0] and DP[7:0]) during a writeback cycle, it must ensure that AHOLD...
User Guide
Page 263
...activities appear transparent to the SMM service routine. The processor enters SMM by the assertion of the SMI# interrupt and the processor's acknowledgment by the Basic Input Output System (BIOS), specialized low-level device drivers, and the operating system. The following the point where... assertion of a system management interrupt (SMI#) and handled by an interrupt service routine. 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 12 System Management Mode (SMM) 12.1 SMM is designed for system control activities such as in real ...
...activities appear transparent to the SMM service routine. The processor enters SMM by the assertion of the SMI# interrupt and the processor's acknowledgment by the Basic Input Output System (BIOS), specialized low-level device drivers, and the operating system. The following the point where... assertion of a system management interrupt (SMI#) and handled by an interrupt service routine. 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 12 System Management Mode (SMM) 12.1 SMM is designed for system control activities such as in real ...