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...AMD-K6™-2E+ Processor 276 Figure 102. Clock Control State Transitions for the AMD-K6™-2E+ Processor-EDX 266 Figure 94. L1 Cache Sector Organization 207 Figure 84. L2 Cache Organization for the AMD-K6™-2E+ Processor-EAX 267 Figure 96. L2 Tag Information for AMD-K6™-2E+ Processor... DR0 271 Figure 101. CLK Waveform 297 Figure 105. 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet List of the AMD-K6™-2E+ Processor 277 Figure 103. Page Flush/Invalidate Register (PFIR 224 Figure 87. L2 Data -...
...AMD-K6™-2E+ Processor 276 Figure 102. Clock Control State Transitions for the AMD-K6™-2E+ Processor-EDX 266 Figure 94. L1 Cache Sector Organization 207 Figure 84. L2 Cache Organization for the AMD-K6™-2E+ Processor-EAX 267 Figure 96. L2 Tag Information for AMD-K6™-2E+ Processor... DR0 271 Figure 101. CLK Waveform 297 Figure 105. 23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet List of the AMD-K6™-2E+ Processor 277 Figure 103. Page Flush/Invalidate Register (PFIR 224 Figure 87. L2 Data -...
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... 287 DC Characteristics for the AMD-K6™-2E+ Processor 287 Power Dissipation for Low-Power AMD-K6™-2E+ Devices . . 289 Power Dissipation for Standard-Power AMD-K6™-2E+ Devices 290 Supported Voltages and Operating Frequencies for LowPower AMD-K6™-2E+ Processors Enabled with AMD PowerNow!™ Technology 290 CLK Switching Characteristics for 100-MHz Bus Operation . 296 CLK...
... 287 DC Characteristics for the AMD-K6™-2E+ Processor 287 Power Dissipation for Low-Power AMD-K6™-2E+ Devices . . 289 Power Dissipation for Standard-Power AMD-K6™-2E+ Devices 290 Supported Voltages and Operating Frequencies for LowPower AMD-K6™-2E+ Processors Enabled with AMD PowerNow!™ Technology 290 CLK Switching Characteristics for 100-MHz Bus Operation . 296 CLK...
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23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 50. Boundary Scan Bit Definitions1 Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/... D51 268 LOCK# 235 A29_E 202 BE1# 169 BRDY# 136 D57 103 D15_E 267 BE0_E 234 A29 201 EADS# 168 STPCLK# 135 D5_E 102 D15 266 BE0# 233 WR_E 200 BE2_E 167 BF2 134 D5 101 D37_E 265 BE5_E 232 W/R# 199 BE2# 166 KEN# 133 D24_E 100 D37 264 BE5# 231...
23542A/0-September 2000 Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet Table 50. Boundary Scan Bit Definitions1 Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/... D51 268 LOCK# 235 A29_E 202 BE1# 169 BRDY# 136 D57 103 D15_E 267 BE0_E 234 A29 201 EADS# 168 STPCLK# 135 D5_E 102 D15 266 BE0# 233 WR_E 200 BE2_E 167 BF2 134 D5 101 D37_E 265 BE5_E 232 W/R# 199 BE2# 166 KEN# 133 D24_E 100 D37 264 BE5# 231...
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... Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU Way 0 Way 1 Way 2 Way 3 512 sets Set 511 Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor Octet 0 Octet 1 Octet 2 Octet 3 Figure 92 shows the L2 cache sector and line organization. Table 53 on the L2 cache is stored in Line... Dword Lower Dword Upper Dword Lower Dword Line 1 Figure 92. Bit 20 of the access, and whether the access is to Figure 93 on page 266). If bit 5 of the address of a cache line equals 1, then this cache line is a function of the instruction executed-RDMSR or WRMSR-and the contents...
... Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU Way 0 Way 1 Way 2 Way 3 512 sets Set 511 Figure 91. L2 Cache Organization for AMD-K6™-2E+ Processor Octet 0 Octet 1 Octet 2 Octet 3 Figure 92 shows the L2 cache sector and line organization. Table 53 on the L2 cache is stored in Line... Dword Lower Dword Upper Dword Lower Dword Line 1 Figure 92. Bit 20 of the access, and whether the access is to Figure 93 on page 266). If bit 5 of the address of a cache line equals 1, then this cache line is a function of the instruction executed-RDMSR or WRMSR-and the contents...
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Dword location is read (as opposed to the L2 data array using data in the format 266 Test and Debug Chapter 13 RDMSR 1 Read tag, line state and LRU information from EAX. When the L2AAR is specified by EDX. This facilitates ...desired cache set 14-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of tag is performed based on the instruction and the T/D bit. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 page 266 describes the operation that is specified by EDX. L2 Tag or Data Location for the...
Dword location is read (as opposed to the L2 data array using data in the format 266 Test and Debug Chapter 13 RDMSR 1 Read tag, line state and LRU information from EAX. When the L2AAR is specified by EDX. This facilitates ...desired cache set 14-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of tag is performed based on the instruction and the T/D bit. Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 page 266 describes the operation that is specified by EDX. L2 Tag or Data Location for the...
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 coherency 222 external address strobe signal 109 hold signal 97 inquire cycles 100, 174 parity 98-99 strobe copy signal ... instruction cache line (figure 207 internal snooping 223 organization 205 write allocate 215 L2 cache cache line (figure 207 cache-line replacement 214 data reads 266 direct access 50 disabling for debug 47 EDX register content 265 Level-2 Cache Array Access Register (L2AAR 50 organization 205 RDMSR instruction effect 265 sector...
Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 coherency 222 external address strobe signal 109 hold signal 97 inquire cycles 100, 174 parity 98-99 strobe copy signal ... instruction cache line (figure 207 internal snooping 223 organization 205 write allocate 215 L2 cache cache line (figure 207 cache-line replacement 214 data reads 266 direct access 50 disabling for debug 47 EDX register content 265 Level-2 Cache Array Access Register (L2AAR 50 organization 205 RDMSR instruction effect 265 sector...
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Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 states (table 221, 225... 265 cache-line fills 214 cache-line replacements 214 coherency 222 data location (figure 51 data reads 266 direct access 50 disabling 211-212 disabling for debug 47 flushing 223 inquire cycles (table 225 least recently... information (figure 52 tag location (figure 51 testing 264 write allocate 215 L2AAR 44, 50, 212-213, 264-266 L3 Cache debugging 263 PCD signal 264 testing 263 Latency, execution (table 23 Layout and Airflow Considerations 317 Level-2 ...
Preliminary Information AMD-K6™-2E+ Embedded Processor Data Sheet 23542A/0-September 2000 states (table 221, 225... 265 cache-line fills 214 cache-line replacements 214 coherency 222 data location (figure 51 data reads 266 direct access 50 disabling 211-212 disabling for debug 47 flushing 223 inquire cycles (table 225 least recently... information (figure 52 tag location (figure 51 testing 264 write allocate 215 L2AAR 44, 50, 212-213, 264-266 L3 Cache debugging 263 PCD signal 264 testing 263 Latency, execution (table 23 Layout and Airflow Considerations 317 Level-2 ...