Product Data Sheet
Page 1
...SSTL_1.8 per cycle, 3-cycle latency specification • 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Caches - Two 64-bit operations per JEDEC - Up to 1 Mbyte ...to 1 GHz (2000 • Electrical Interfaces MT/s) or 4 Gigabytes/s in each core • Refer to the AMD NPT 0Fh Family Processor Electrical Data Sheet, order# 31119, for processor - Lidded ... Check Architecture - HyperTransport™ technology: LVDS-like electrical specifications - AMD Athlon™ X2 Dual-Core Processor Product Data Sheet • Compatible with lead used only in small amounts...
...SSTL_1.8 per cycle, 3-cycle latency specification • 64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Caches - Two 64-bit operations per JEDEC - Up to 1 Mbyte ...to 1 GHz (2000 • Electrical Interfaces MT/s) or 4 Gigabytes/s in each core • Refer to the AMD NPT 0Fh Family Processor Electrical Data Sheet, order# 31119, for processor - Lidded ... Check Architecture - HyperTransport™ technology: LVDS-like electrical specifications - AMD Athlon™ X2 Dual-Core Processor Product Data Sheet • Compatible with lead used only in small amounts...