DH61DL Technical Product Specification
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... for APs End CPU SMM Init CPU DXE Phase 0x47 CPU DXE Phase begin 0x48 Refresh memory space attributes according to MTRRs 0x49 Load the microcode if needed 0x4A Initialize strings to HII database 0x4B 0x4C Initialize MP support CPU DXE Phase End CPU DXE SMM Phase 0x4D CPU DXE SMM Phase... begin 0x4E Relocate SM bases for all APs 0x4F CPU DXE SMM Phase end I/O Buses 0x50 Enumerating PCI buses 0x51 0x52 Allocating ...
... for APs End CPU SMM Init CPU DXE Phase 0x47 CPU DXE Phase begin 0x48 Refresh memory space attributes according to MTRRs 0x49 Load the microcode if needed 0x4A Initialize strings to HII database 0x4B 0x4C Initialize MP support CPU DXE Phase End CPU DXE SMM Phase 0x4D CPU DXE SMM Phase... begin 0x4E Relocate SM bases for all APs 0x4F CPU DXE SMM Phase end I/O Buses 0x50 Enumerating PCI buses 0x51 0x52 Allocating ...