Manual/User Guide
Page 16
... out burst 5-144 5.6.4 Power-on and reset 5-145 CHAPTER 6 Operations 6-1 6.1 Device Response to the Reset 6-2 6.1.1 Response to power-on 6-2 6.1.2 Response to hardware reset 6-3 6.1.3 Response to software reset 6-5 6.1.4 Response to diagnostic command 6-6 xii C141-E195-02EN
... out burst 5-144 5.6.4 Power-on and reset 5-145 CHAPTER 6 Operations 6-1 6.1 Device Response to the Reset 6-2 6.1.1 Response to power-on 6-2 6.1.2 Response to hardware reset 6-3 6.1.3 Response to software reset 6-5 6.1.4 Response to diagnostic command 6-6 xii C141-E195-02EN
Manual/User Guide
Page 19
... 5-144 Figure 5.21 Power-on Reset Timing 5-145 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Response to power-on 6-3 Response to hardware reset 6-4 Response to software reset 6-5 Response to diagnostic command 6-6 Sector slip processing 6-10 Automatic alternating processing 6-11 Data buffer structure 6-12 C141-E195-02EN xv
... 5-144 Figure 5.21 Power-on Reset Timing 5-145 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Response to power-on 6-3 Response to hardware reset 6-4 Response to software reset 6-5 Response to diagnostic command 6-6 Sector slip processing 6-10 Automatic alternating processing 6-11 Data buffer structure 6-12 C141-E195-02EN xv
Manual/User Guide
Page 84
... command block and writing a command code in the task register. - Interface (2) Device Control register (X'3F6') The Device Control register contains device interrupt and software reset. Bit 7: High Order Byte (HOB) is in the highimpedance state. 5.3 Host Commands The host system issues a command to the command register, ... Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to 24 and the higher-order 8 bits of hardware or software reset. The device can halt the uncompleted command execution only at execution of the sector count are written. 5-14 C141-E195-02EN
... command block and writing a command code in the task register. - Interface (2) Device Control register (X'3F6') The Device Control register contains device interrupt and software reset. Bit 7: High Order Byte (HOB) is in the highimpedance state. 5.3 Host Commands The host system issues a command to the command register, ... Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to 24 and the higher-order 8 bits of hardware or software reset. The device can halt the uncompleted command execution only at execution of the sector count are written. 5-14 C141-E195-02EN
Manual/User Guide
Page 114
...modes Features Register X'02' X'03' X'05' X'42' X'55' X'66' X'82' X'85' X'AA' X'BB' X'C2' X'CC' Drive operation mode Enables the write cache function. At power-on or after hardware reset, the default mode is done. Write cashe function : Enabled Transfer mode...keeping Read cashe function : Enabled 5-44 C141-E195-02EN Enables the read cache function. Disables the reverting to power-on default settings after software reset. (*1) Disables the write cache function. Set the data transfer mode. *1 Enables the advanced power management function. *2 Enables the Acoustic ...
...modes Features Register X'02' X'03' X'05' X'42' X'55' X'66' X'82' X'85' X'AA' X'BB' X'C2' X'CC' Drive operation mode Enables the write cache function. At power-on or after hardware reset, the default mode is done. Write cashe function : Enabled Transfer mode...keeping Read cashe function : Enabled 5-44 C141-E195-02EN Enables the read cache function. Disables the reverting to power-on default settings after software reset. (*1) Disables the write cache function. Set the data transfer mode. *1 Enables the advanced power management function. *2 Enables the Acoustic ...
Manual/User Guide
Page 117
..., the value is stored for "Performance mode", and low-speed seek by the SET MULTIPLE MODE command. Setting the seek mode by the drive across power on, hardware and software resets. 5.3 Host Commands *3) Automatic Acoustic Management (AAM) The host writes to which the seek sound is suppressed operates as the block counts...
..., the value is stored for "Performance mode", and low-speed seek by the SET MULTIPLE MODE command. Setting the seek mode by the drive across power on, hardware and software resets. 5.3 Host Commands *3) Automatic Acoustic Management (AAM) The host writes to which the seek sound is suppressed operates as the block counts...
Manual/User Guide
Page 135
... motor is stopped and the ATA interface section is the only way to make the device enter the sleep mode. All I /O registers contents to execute a software or hardware reset. The only way to release the device from sleep mode is to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL...
... motor is stopped and the ATA interface section is the only way to make the device enter the sleep mode. All I /O registers contents to execute a software or hardware reset. The only way to release the device from sleep mode is to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL...
Manual/User Guide
Page 162
...) The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. If a Host Protected Area has been set by a hardware or software reset. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE...
...) The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings. If a Host Protected Area has been set by a hardware or software reset. After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command, all DEVICE CONFIGURATION SET, DEVICE CONFIGURATION FREEZE LOCK, DEVICE CONFIGURATION IDENTIFY, and DEVICE CONFIGURATION RESTORE...
Manual/User Guide
Page 188
...time. All of the control signals are redefined to the device. Ownership of DD (15:0) and this protocol is used for data transfers so that drives the data onto the bus. Both edges of STROBE are used there are issued by a host to latch the data. An Ultra DMA capable ...DMA feature and the Ultra DMA Modes the device is capable of supporting. During an Ultra DMA burst a sender shall always drive data onto the bus, and after executing a Software reset sequence. When this protocol is enabled it shall be satisfied. These lines assume these commands are no changes to the Ultra...
...time. All of the control signals are redefined to the device. Ownership of DD (15:0) and this protocol is used for data transfers so that drives the data onto the bus. Both edges of STROBE are used there are issued by a host to latch the data. An Ultra DMA capable ...DMA feature and the Ultra DMA Modes the device is capable of supporting. During an Ultra DMA burst a sender shall always drive data onto the bus, and after executing a Software reset sequence. When this protocol is enabled it shall be satisfied. These lines assume these commands are no changes to the Ultra...
Manual/User Guide
Page 215
5.6 Timing 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESETSoftware reset BSY tM tN DASPtP *1: Reset means including Power-on... 25 - µs - 400 ns - 1 ms - 30 s - 400 ms - 31 s Figure 5.21 Power-on -Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) [Master device] BSY DASP- [Slave device] BSY PDIAG- DASP- assertion Min. assertion (slave device) tS Duration of RESETtN Time from RESET...
5.6 Timing 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESETSoftware reset BSY tM tN DASPtP *1: Reset means including Power-on... 25 - µs - 400 ns - 1 ms - 30 s - 400 ms - 31 s Figure 5.21 Power-on -Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) [Master device] BSY DASP- [Slave device] BSY PDIAG- DASP- assertion Min. assertion (slave device) tS Duration of RESETtN Time from RESET...
Manual/User Guide
Page 221
... is not received. Max. 1 ms. Max. 30 sec. signal when negating the PDIAG- signal. After the slave device receives the software reset, the slave device shall report its presence and the result of the self-diagnostics to see if the slave device has completed the ...master device checks the PDIAG- 6.1 Device Response to the Reset 6.1.3 Response to software reset C141-E195-02EN 6-5 If a slave device is checked for a software reset. Slave device BSY bit PDIAGDASP- Figure 6.3 Response to software reset The master device does not check the DASP- signal for up to 15...
... is not received. Max. 1 ms. Max. 30 sec. signal when negating the PDIAG- signal. After the slave device receives the software reset, the slave device shall report its presence and the result of the self-diagnostics to see if the slave device has completed the ...master device checks the PDIAG- 6.1 Device Response to the Reset 6.1.3 Response to software reset C141-E195-02EN 6-5 If a slave device is checked for a software reset. Slave device BSY bit PDIAGDASP- Figure 6.3 Response to software reset The master device does not check the DASP- signal for up to 15...
Manual/User Guide
Page 224
...still stayed in the standby mode. • Reset (hardware or software) • STANDBY command • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command • CHECK POWER MODE command (5) Sleep mode The power consumption of the drive is issued in this mode. However if a command with disk access...standby mode is ignored.) 6-8 C141-E195-02EN The only method to return from the sleep mode. Operations • Upon receipt of a hard reset • Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the device does not accept the command. (It is ...
...still stayed in the standby mode. • Reset (hardware or software) • STANDBY command • STANDBY IMMEDIATE command • INITIALIZE DEVICE PARAMETERS command • CHECK POWER MODE command (5) Sleep mode The power consumption of the drive is issued in this mode. However if a command with disk access...standby mode is ignored.) 6-8 C141-E195-02EN The only method to return from the sleep mode. Operations • Upon receipt of a hard reset • Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the device does not accept the command. (It is ...
Manual/User Guide
Page 244
..., 6-2 reset response 6-20 reset timing 5-145 resistor, pull-up or pull-down 5-129 response, to diagnostic command 6-6 hardware reset 6-3 power-on 6-2 software reset 6-5 response to diagnostic command 6-6 hardware reset 6-3 power-on 6-2 software reset 6-5 S sector slip processing 6-10 sequential command 6-16 sequential hit 6-16 sleep mode 6-8 spare area 6-9 standby mode 6-8 status report in...
..., 6-2 reset response 6-20 reset timing 5-145 resistor, pull-up or pull-down 5-129 response, to diagnostic command 6-6 hardware reset 6-3 power-on 6-2 software reset 6-5 response to diagnostic command 6-6 hardware reset 6-3 power-on 6-2 software reset 6-5 S sector slip processing 6-10 sequential command 6-16 sequential hit 6-16 sleep mode 6-8 spare area 6-9 standby mode 6-8 status report in...