English Manual.
Page 41
... Copyright (C) 1985-2006, American Megatrends, Inc. Select [Limit], the DRAM speed will not exceed the specified value listed in clock cycles) between the CAS# and RAS# strobe signals. 34 The available settings are : [400MHz], [533MHz...must initialize the frequency of the target clock frequency. Select [Manual], then DRAM speed is determined from the supported CAS latencies at the specified "Memory Speed Adjust" speed. Otherwise, SPD value is a small EEPROM chip... is set value of each DCT in AM2+ CPU. ► tCL (CAS Latency) The number of DRAM timing by SPD device.
... Copyright (C) 1985-2006, American Megatrends, Inc. Select [Limit], the DRAM speed will not exceed the specified value listed in clock cycles) between the CAS# and RAS# strobe signals. 34 The available settings are : [400MHz], [533MHz...must initialize the frequency of the target clock frequency. Select [Manual], then DRAM speed is determined from the supported CAS latencies at the specified "Memory Speed Adjust" speed. Otherwise, SPD value is a small EEPROM chip... is set value of each DCT in AM2+ CPU. ► tCL (CAS Latency) The number of DRAM timing by SPD device.