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The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence may contain design defects or errors known as the property of others. Check with your PC manufacturer on your product order. ΔIntel processor numbers are ...INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. See http://www.intel.com/products/processor_number for conflicts or incompatibilities arising from published specifications. Designers must not rely on which may be compatible with all operating systems....
The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence may contain design defects or errors known as the property of others. Check with your PC manufacturer on your product order. ΔIntel processor numbers are ...INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. See http://www.intel.com/products/processor_number for conflicts or incompatibilities arising from published specifications. Designers must not rely on which may be compatible with all operating systems....
Data Sheet
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... Zones 35 3.3 Package Loading Specifications 35 3.4 Package Handling Guidelines 35 3.5 Package Insertion Specifications 36 3.6 Processor Mass Specification 36 3.7 Processor Materials 36 3.8 Processor Markings 36 3.9 Processor Land Coordinates 38 4 Land Listing and Signal Descriptions 39 4.1 Processor Land Assignments 39 4.2 Alphabetical Signals Reference 62 5 Thermal Specifications and Design Considerations 71 5.1 Processor Thermal Specifications 71 5.1.1 Thermal Specifications 71 5.1.2 Thermal Metrology 76 5.2 Processor Thermal Features 76 5.2.1 Thermal...
... Zones 35 3.3 Package Loading Specifications 35 3.4 Package Handling Guidelines 35 3.5 Package Insertion Specifications 36 3.6 Processor Mass Specification 36 3.7 Processor Materials 36 3.8 Processor Markings 36 3.9 Processor Land Coordinates 38 4 Land Listing and Signal Descriptions 39 4.1 Processor Land Assignments 39 4.2 Alphabetical Signals Reference 62 5 Thermal Specifications and Design Considerations 71 5.1 Processor Thermal Specifications 71 5.1.1 Thermal Specifications 71 5.1.2 Thermal Metrology 76 5.2 Processor Thermal Features 76 5.2.1 Thermal...
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... Heatsink Attach Clip Assembly .....90 7.2 Electrical Requirements 90 7.2.1 Fan Heatsink Power Supply 90 7.3 Thermal Specifications 92 7.3.1 7.3.2 7.3.3 Boxed Processor Cooling Requirements 92 Fan Speed Control Operation (Intel® Core™2 Extreme processors only) .........94 Fan Speed Control Operation (Intel® Core™2 Quad processor 94 8 Debug Tools Specifications 97 8.1 Logic Analyzer Interface (LAI 97 8.1.1 Mechanical Considerations 97 8.1.2 Electrical Considerations 97 4 Datasheet
... Heatsink Attach Clip Assembly .....90 7.2 Electrical Requirements 90 7.2.1 Fan Heatsink Power Supply 90 7.3 Thermal Specifications 92 7.3.1 7.3.2 7.3.3 Boxed Processor Cooling Requirements 92 Fan Speed Control Operation (Intel® Core™2 Extreme processors only) .........94 Fan Speed Control Operation (Intel® Core™2 Quad processor 94 8 Debug Tools Specifications 97 8.1 Logic Analyzer Interface (LAI 97 8.1.1 Mechanical Considerations 97 8.1.2 Electrical Considerations 97 4 Datasheet
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... Example Waveform 21 3 Differential Clock Waveform 29 4 Differential Clock Crosspoint Specification 30 5 Differential Measurements 30 6 Processor Package Assembly Sketch 31 7 Processor Package Drawing Sheet 1 of 3 32 8 Processor Package Drawing Sheet 2 of 3 33 9 Processor Package Drawing Sheet 3 of the Boxed Processor 87 23 Space Requirements for the Boxed Processor (Side View 88 24 Space Requirements for the Boxed...
... Example Waveform 21 3 Differential Clock Waveform 29 4 Differential Clock Crosspoint Specification 30 5 Differential Measurements 30 6 Processor Package Assembly Sketch 31 7 Processor Package Drawing Sheet 1 of 3 32 8 Processor Package Drawing Sheet 2 of 3 33 9 Processor Package Drawing Sheet 3 of the Boxed Processor 87 23 Space Requirements for the Boxed Processor (Side View 88 24 Space Requirements for the Boxed...
Data Sheet
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... 15 Core Frequency to FSB Multiplier Configuration 26 16 BSEL[2:0] Frequency Table for BCLK[1:0 27 17 Front Side Bus Differential BCLK Specifications 28 18 FSB Differential Clock Specifications (1066 MHz FSB 28 19 FSB Differential Clock Specifications (1333 MHz FSB 29 20 Processor Loading Specifications 35 ... 42 24 Numerical Land Assignment 52 25 Signal Description...62 26 Processor Thermal Specifications 72 27 Thermal Profile for 130 W Processors 73 28 Thermal Profile for 105 W Processors 74 29 Thermal Profile 95 W Processors 75 30 GetTemp0() and GetTemp1() Error Codes 81 31 Power-...
... 15 Core Frequency to FSB Multiplier Configuration 26 16 BSEL[2:0] Frequency Table for BCLK[1:0 27 17 Front Side Bus Differential BCLK Specifications 28 18 FSB Differential Clock Specifications (1066 MHz FSB 28 19 FSB Differential Clock Specifications (1333 MHz FSB 29 20 Processor Loading Specifications 35 ... 42 24 Numerical Land Assignment 52 25 Signal Description...62 26 Processor Thermal Specifications 72 27 Thermal Profile for 130 W Processors 73 28 Thermal Profile for 105 W Processors 74 29 Thermal Profile 95 W Processors 75 30 GetTemp0() and GetTemp1() Error Codes 81 31 Power-...
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... 24. • Updated Table 29, "Fan Heatsink Power and Signal Specifications". • Added specifications for the Intel® Core™2 Quad Processor Q6700 and Intel® Core™2 Extreme quad-core processor QX6850 • Added Intel® Core™2 Quad Processor Q6600 for 775_VR_CONFIG_05A • Added Intel® Core™2 Extreme quad-core processor QX6850 • Added Intel® Core™2 Extreme quad-core processor QX6800 § Date November 2006 January 2007 July 2007 July 2007...
... 24. • Updated Table 29, "Fan Heatsink Power and Signal Specifications". • Added specifications for the Intel® Core™2 Quad Processor Q6700 and Intel® Core™2 Extreme quad-core processor QX6850 • Added Intel® Core™2 Quad Processor Q6600 for 775_VR_CONFIG_05A • Added Intel® Core™2 Extreme quad-core processor QX6850 • Added Intel® Core™2 Extreme quad-core processor QX6800 § Date November 2006 January 2007 July 2007 July 2007...
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... mechanical features for heatsink attach, a retention mechanism is the generic form of the Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence. Refers to as interrupt messages pass between the processor and system core logic (a.k.a. Quad core processor in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are explained here...
... mechanical features for heatsink attach, a retention mechanism is the generic form of the Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence. Refers to as interrupt messages pass between the processor and system core logic (a.k.a. Quad core processor in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are explained here...
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... http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ § § Datasheet 11 References Document Intel® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update Intel® Core™2 Extreme Quad-Core Processor and Intel® Core™2 Quad Processor Thermal and...
... http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ http://www.intel.com/ products/processor/manuals/ § § Datasheet 11 References Document Intel® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update Intel® Core™2 Extreme Quad-Core Processor and Intel® Core™2 Quad Processor Thermal and...
Data Sheet
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... system ground plane. VTT Decoupling Decoupling must be connected to the processor remains within specifications during longer lasting changes in timing violations or reduced lifetime of the processor interfaces and signals. This includes bulk capacitance with the power delivery ...of generating large current swings. In addition, ceramic decoupling capacitors are provided. Decoupling Guidelines Due to satisfy the processor voltage specifications. This may cause voltages on -chip power distribution. A conservative decoupling solution would consist of a combination of ...
... system ground plane. VTT Decoupling Decoupling must be connected to the processor remains within specifications during longer lasting changes in timing violations or reduced lifetime of the processor interfaces and signals. This includes bulk capacitance with the power delivery ...of generating large current swings. In addition, ceramic decoupling capacitors are provided. Decoupling Guidelines Due to satisfy the processor voltage specifications. This may cause voltages on -chip power distribution. A conservative decoupling solution would consist of a combination of ...
Data Sheet
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... [A]GTL+ bus operation. Table 4 includes VID step sizes and DC shift ranges. DC specifications for further details on specific valid core frequency and VID values of the processor. Refer to the Intel® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update for dynamic VID transitions are not permitted. Refer to Table 12 for...
... [A]GTL+ bus operation. Table 4 includes VID step sizes and DC shift ranges. DC specifications for further details on specific valid core frequency and VID values of the processor. Refer to the Intel® Core™2 Extreme Quad-Core Processor QX6000 Sequence and Intel® Core™2 Quad Processor Q6000 Sequence Specification Update for dynamic VID transitions are not permitted. Refer to Table 12 for...
Data Sheet
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... 0 1 0 1 0 1 1.3500 0 1 0 1 0 0 1.3625 0 1 0 0 1 1 1.3750 0 1 0 0 1 0 1.3875 0 1 0 0 0 1 1.4000 0 1 0 0 0 0 1.4125 0 0 1 1 1 1 1.4250 0 0 1 1 1 0 1.4375 0 0 1 1 0 1 1.4500 0 0 1 1 0 0 1.4625 0 0 1 0 1 1 1.4750 0 0 1 0 1 0 1.4875 0 0 1 0 0 1 1.5000 0 0 1 0 0 0 1.5125 0 0 0 1 1 1 1.5250 0 0 0 1 1 0 1.5375 0 0 0 1 0 1 1.5500 0 0 0 1 0 0 1.5625 0 0 0 0 1 1 1.5750 0 0 0 0 1 0 1.5875 0 0 0 0 0 1 1.6000 0 0 0 0 0 0 OFF Datasheet 15 Electrical Specifications Table 2.
... 0 1 0 1 0 1 1.3500 0 1 0 1 0 0 1.3625 0 1 0 0 1 1 1.3750 0 1 0 0 1 0 1.3875 0 1 0 0 0 1 1.4000 0 1 0 0 0 0 1.4125 0 0 1 1 1 1 1.4250 0 0 1 1 1 0 1.4375 0 0 1 1 0 1 1.4500 0 0 1 1 0 0 1.4625 0 0 1 0 1 1 1.4750 0 0 1 0 1 0 1.4875 0 0 1 0 0 1 1.5000 0 0 1 0 0 0 1.5125 0 0 0 1 1 1 1.5250 0 0 0 1 1 0 1.5375 0 0 0 1 0 1 1.5500 0 0 0 1 0 0 1.5625 0 0 0 0 1 1 1.5750 0 0 0 0 1 0 1.5875 0 0 0 0 0 1 1.6000 0 0 0 0 0 0 OFF Datasheet 15 Electrical Specifications Table 2.
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Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must ...other signal (including each group: • TESTHI[1:0] • TESTHI[7:2] • TESTHI10 - cannot be within the processor silicon. cannot be grouped together as the on -die termination. However, see Table 14. The TESTHI signals may interfere.... Unused outputs can result in component malfunction or incompatibility with other ) can be terminated on the processor silicon. Resistor values should be connected through a resistor to VTT via a pull-up resistors of the...
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must ...other signal (including each group: • TESTHI[1:0] • TESTHI[7:2] • TESTHI10 - cannot be within the processor silicon. cannot be grouped together as the on -die termination. However, see Table 14. The TESTHI signals may interfere.... Unused outputs can result in component malfunction or incompatibility with other ) can be terminated on the processor silicon. Resistor values should be connected through a resistor to VTT via a pull-up resistors of the...
Data Sheet
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Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1,2 VCC Core voltage with respect to VSS -0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature -40 85 °C 3, 4, 5 NOTES: 1. Storage ...avoid high static voltages or electric fields. This rating applies to the processor case temperature specifications. 4. Failure to adhere to the processor. 3. Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings...
Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1,2 VCC Core voltage with respect to VSS -0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature -40 85 °C 3, 4, 5 NOTES: 1. Storage ...avoid high static voltages or electric fields. This rating applies to the processor case temperature specifications. 4. Failure to adhere to the processor. 3. Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings...
Data Sheet
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... mm. A variable voltage source should be altered. The voltage specification requirements are calibrated during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). 4. The processor should not be drawn from the system is set at the socket... stable ICC for the processor are targets only. Adherence to Table 5 and Figure 1 V 4, 5, 6 QX6700 2.66 GHz Q6700 2.66 GHz Q6600 2.40 GHz VCC_BOOT VCCPLL ICC Default VCC voltage for GTLREF - -- 200 μA NOTES: 1. These processors have different settings within the...
... mm. A variable voltage source should be altered. The voltage specification requirements are calibrated during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT State). 4. The processor should not be drawn from the system is set at the socket... stable ICC for the processor are targets only. Adherence to Table 5 and Figure 1 V 4, 5, 6 QX6700 2.66 GHz Q6700 2.66 GHz Q6600 2.40 GHz VCC_BOOT VCCPLL ICC Default VCC voltage for GTLREF - -- 200 μA NOTES: 1. These processors have different settings within the...
Data Sheet
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... regulation feedback for socket loadline guidelines and VR implementation details. 4. Electrical Specifications 8. Refer to Figure 1 for overshoot allowed as the maximum ICC for the processor. 11.VTT must be connected to this loadline specification is based on the VCC_MAX loadline. ICC_MAX specification is based on design characterization and is measured at the VCC_SENSE and...
... regulation feedback for socket loadline guidelines and VR implementation details. 4. Electrical Specifications 8. Refer to Figure 1 for overshoot allowed as the maximum ICC for the processor. 11.VTT must be connected to this loadline specification is based on the VCC_MAX loadline. ICC_MAX specification is based on design characterization and is measured at the VCC_SENSE and...
Data Sheet
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... at the die measured at the VCC_SENSE and VSS_SENSE lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for overshoot allowed as shown in Section 2.5.3. 2. Voltage regulation feedback ...100 110 120 Vcc Maximum Vcc Typical Vcc Minimum Vcc [V] NOTES: 1. This loadline specification shows the deviation from processor VCC and VSS lands. Electrical Specifications Figure 1. The loadline specification includes both static and transient limits except for socket loadline guidelines and VR implementation details...
... at the die measured at the VCC_SENSE and VSS_SENSE lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for overshoot allowed as shown in Section 2.5.3. 2. Voltage regulation feedback ...100 110 120 Vcc Maximum Vcc Typical Vcc Minimum Vcc [V] NOTES: 1. This loadline specification shows the deviation from processor VCC and VSS lands. Electrical Specifications Figure 1. The loadline specification includes both static and transient limits except for socket loadline guidelines and VR implementation details...
Data Sheet
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...that are < 10 ns in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. These measurements of processor die level overshoot must meet the specifications in duration may be taken with a bandwidth limited oscilloscope set to a greater than or equal to low ... VOS_MAX (VOS_MAX is measured overshoot voltage. 2. Adherence to these specifications is measured time duration above VID 2.5.4 NOTES: 1. Die Voltage Validation Overshoot events on processor must be ignored. VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID ...
...that are < 10 ns in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. These measurements of processor die level overshoot must meet the specifications in duration may be taken with a bandwidth limited oscilloscope set to a greater than or equal to low ... VOS_MAX (VOS_MAX is measured overshoot voltage. 2. Adherence to these specifications is measured time duration above VID 2.5.4 NOTES: 1. Die Voltage Validation Overshoot events on processor must be ignored. VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID ...
Data Sheet
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... when receiving. The GTL+ inputs require a reference voltage (GTLREF) which is used by buffer type. Intel chipsets will also provide on the motherboard for each processor (and chipset), separate VCC and VTT supplies are necessary. With the implementation of 2) Signal Group Type ...comes the need to terminate the bus on -die termination, thus eliminating the need to VTT. Electrical Specifications 2.6 2.6.1 Table 7. Signaling Specifications Most processor Front Side Bus signals use GTLREF[3:0] as the GTL+ I/O group when driving. Platforms implement a termination voltage level for...
... when receiving. The GTL+ inputs require a reference voltage (GTLREF) which is used by buffer type. Intel chipsets will also provide on the motherboard for each processor (and chipset), separate VCC and VTT supplies are necessary. With the implementation of 2) Signal Group Type ...comes the need to terminate the bus on -die termination, thus eliminating the need to VTT. Electrical Specifications 2.6 2.6.1 Table 7. Signaling Specifications Most processor Front Side Bus signals use GTLREF[3:0] as the GTL+ I/O group when driving. Platforms implement a termination voltage level for...
Data Sheet
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Electrical Specifications Table 7. . Table 9. In systems with No RTT A20M#, BCLK[1:0], BSEL[2:0], COMP... port is open drain output and CMOS input. FSB Signal Groups (Sheet 2 of RESET# defines the processor configuration options. The value of these signals are actively driven to -inactive edge of 2) Signal Group Type...LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TMS1, TRST#1 NOTES: 1. In processor systems where no connects. 3. Refer to the reference voltage. PROCHOT# signal type is implemented on the system board, these signals ...
Electrical Specifications Table 7. . Table 9. In systems with No RTT A20M#, BCLK[1:0], BSEL[2:0], COMP... port is open drain output and CMOS input. FSB Signal Groups (Sheet 2 of RESET# defines the processor configuration options. The value of these signals are actively driven to -inactive edge of 2) Signal Group Type...LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TMS1, TRST#1 NOTES: 1. In processor systems where no connects. 3. Refer to the reference voltage. PROCHOT# signal type is implemented on the system board, these signals ...
Data Sheet
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... 16 50 mA 3 ILO Output Leakage Current N/A ± 200 µA 4 NOTES: 1. Measured at the processor core (pads) unless otherwise stated. See Section 2.6.3 for entering and leaving the low power states. 2.6.3 Table 10. Unless otherwise noted, all specifications in these specifications is defined as the voltage range at a receiving agent that will be asserted/ deasserted...
... 16 50 mA 3 ILO Output Leakage Current N/A ± 200 µA 4 NOTES: 1. Measured at the processor core (pads) unless otherwise stated. See Section 2.6.3 for entering and leaving the low power states. 2.6.3 Table 10. Unless otherwise noted, all specifications in these specifications is defined as the voltage range at a receiving agent that will be asserted/ deasserted...