Data Sheet
Page 2
...177; Intel® Virtualization Technology requires a computer system with your PC manufacturer on your hardware and software configurations. Enabling Execute Disable Bit functionality requires a PC with a processor with a processor, chipset, BIOS, operating system, device drivers, and ... time, without an Intel 64-enabled BIOS. Intel® 64 requires a computer system with Execute Disable Bit capability and a supporting operating system. The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence may require...
...177; Intel® Virtualization Technology requires a computer system with your PC manufacturer on your hardware and software configurations. Enabling Execute Disable Bit functionality requires a PC with a processor with a processor, chipset, BIOS, operating system, device drivers, and ... time, without an Intel 64-enabled BIOS. Intel® 64 requires a computer system with Execute Disable Bit capability and a supporting operating system. The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence may require...
Data Sheet
Page 26
...processor clocking, contact your Intel field representative. For more information on the system board using high precision voltage divider circuits. Table 14 lists the GTLREF specifications. The processor bus ratio multiplier will be provided on -die termination. The processor uses a differential clocking implementation. Refer to FSB Frequency Core... as the core frequency of the processor. See Table 8 for implementation details. 3. COMP resistance must be set at VTT/3 of the GTL+ output driver. 4. Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0]...
...processor clocking, contact your Intel field representative. For more information on the system board using high precision voltage divider circuits. Table 14 lists the GTLREF specifications. The processor bus ratio multiplier will be provided on -die termination. The processor uses a differential clocking implementation. Refer to FSB Frequency Core... as the core frequency of the processor. See Table 8 for implementation details. 3. COMP resistance must be set at VTT/3 of the GTL+ output driver. 4. Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0]...
Data Sheet
Page 29
...be between successive crossover voltages. Measurement taken from a 3 ns period and a +0.5% maximum variance due to the CK505 Clock Synthesizer/Driver Specification. 5. Max period specification is based on a 333 MHz BCLK[1:0]. 2. Slew rate matching is the average period. The ...largest absolute difference between adjacent clock periods must be less than the period stability. 6. Figure 3. Unless otherwise noted, all processor core frequencies based on the summation of +300 PPM deviation from differential waveform. 7. Differential Clock Waveform CLK 0 VCROSS Median +...
...be between successive crossover voltages. Measurement taken from a 3 ns period and a +0.5% maximum variance due to the CK505 Clock Synthesizer/Driver Specification. 5. Max period specification is based on a 333 MHz BCLK[1:0]. 2. Slew rate matching is the average period. The ...largest absolute difference between adjacent clock periods must be less than the period stability. 6. Figure 3. Unless otherwise noted, all processor core frequencies based on the summation of +300 PPM deviation from differential waveform. 7. Differential Clock Waveform CLK 0 VCROSS Median +...
Data Sheet
Page 64
... D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 DBI[3:0]# Furthermore, the DBI# signals determine the polarity of 9) Name Type Description D[63:0]# (Data) are quad-pumped signals and will, thus, be driven four times in a common clock period. When the DBI# signal is active, the corresponding data group is de...bus is released after DBSY# is inverted and therefore sampled active high. The data driver asserts DRDY# to indicate that the data bus is used only in use. DBR# is in processor systems where no connect in -target probe can drive system reset. Signal Description (...
... D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 DBI[3:0]# Furthermore, the DBI# signals determine the polarity of 9) Name Type Description D[63:0]# (Data) are quad-pumped signals and will, thus, be driven four times in a common clock period. When the DBI# signal is active, the corresponding data group is de...bus is released after DBSY# is inverted and therefore sampled active high. The data driver asserts DRDY# to indicate that the data bus is used only in use. DBR# is in processor systems where no connect in -target probe can drive system reset. Signal Description (...
Data Sheet
Page 65
... are signals that a transaction cannot be guaranteed in-order completion. When STPCLK# is asserted by the data driver on each data transfer, indicating valid data on the data bus. The assertion of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. For additional information on the...
... are signals that a transaction cannot be guaranteed in-order completion. When STPCLK# is asserted by the data driver on each data transfer, indicating valid data on the data bus. The assertion of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. For additional information on the...
Data Sheet
Page 77
... to -FSB multiple utilized by issuing a new VID code to service any additional hardware, software drivers, or interrupt handling routines. When the TCC is activated, the processor automatically transitions to the normal system operating point. Once the temperature has dropped below the maximum operating ...active continuously. Refer to reach the target operating voltage. During the voltage change, it will transition to the new core operating voltage by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID is that specified in Table 4. Once the new operating ...
... to -FSB multiple utilized by issuing a new VID code to service any additional hardware, software drivers, or interrupt handling routines. When the TCC is activated, the processor automatically transitions to the normal system operating point. Once the temperature has dropped below the maximum operating ...active continuously. Refer to reach the target operating voltage. During the voltage change, it will transition to the new core operating voltage by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID is that specified in Table 4. Once the new operating ...