Data Sheet
Page 2
...others. Intel, Pentium, Itanium, Xeon, Intel SpeedStep, andand the Intel logo are not a measure of Intel Corporation in any features or instructions marked "reserved" or "undefined." The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 ... supporting operating system. See http://www.intel.com/technology/intel64/index.htm for it. Enabling Execute Disable Bit functionality requires a PC with a processor with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for more information ...
...others. Intel, Pentium, Itanium, Xeon, Intel SpeedStep, andand the Intel logo are not a measure of Intel Corporation in any features or instructions marked "reserved" or "undefined." The Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 ... supporting operating system. See http://www.intel.com/technology/intel64/index.htm for it. Enabling Execute Disable Bit functionality requires a PC with a processor with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for more information ...
Data Sheet
Page 26
... board using high precision voltage divider circuits. As in this table apply to all specifications in previous generation processors, the processor's core frequency is a multiple of the BCLK[1:0] frequency. COMP resistance must be generated on the system board with...GHz 4.00 GHz - The processor uses a differential clocking implementation. GTLREF is the on the processor clocking, contact your Intel field representative. For more information on -die termination resistance measured at VTT/3 of the GTL+ output driver. 4. Individual processors operate only at its default ...
... board using high precision voltage divider circuits. As in this table apply to all specifications in previous generation processors, the processor's core frequency is a multiple of the BCLK[1:0] frequency. COMP resistance must be generated on the system board with...GHz 4.00 GHz - The processor uses a differential clocking implementation. GTLREF is the on the processor clocking, contact your Intel field representative. For more information on -die termination resistance measured at VTT/3 of the GTL+ output driver. 4. Individual processors operate only at its default ...
Data Sheet
Page 29
...difference between 40 and 60%. 3. The median cross point is used to calculate the voltage thresholds the oscilloscope is to the CK505 Clock Synthesizer/Driver Specification. 5. Differential Clock Waveform CLK 0 VCROSS Median + 75 mV VCROSS V median CROSS Median - 75 mV CLK 1 VCROSS Max ...period stability is based on a 333 MHz BCLK[1:0]. 2. A given period may vary from differential waveform. 7. In this table apply to all processor core frequencies based on the summation of +300 PPM deviation from a 3 ns period. In other words, the largest absolute difference between adjacent clock...
...difference between 40 and 60%. 3. The median cross point is used to calculate the voltage thresholds the oscilloscope is to the CK505 Clock Synthesizer/Driver Specification. 5. Differential Clock Waveform CLK 0 VCROSS Median + 75 mV VCROSS V median CROSS Median - 75 mV CLK 1 VCROSS Max ...period stability is based on a 333 MHz BCLK[1:0]. 2. A given period may vary from differential waveform. 7. In this table apply to all processor core frequencies based on the summation of +300 PPM deviation from a 3 ns period. In other words, the largest absolute difference between adjacent clock...
Data Sheet
Page 64
... active, the corresponding data group is a no debug port is in use. If a debug port is implemented in the system. The data driver asserts DRDY# to a pair of the D[63:0]# signals.The DBI[3:0]# signals are source synchronous and indicate the polarity of one DSTBP# and ... determine the polarity of 9) Name Type Description D[63:0]# (Data) are quad-pumped signals and will, thus, be driven four times in -target probe can drive system reset. D[63:0]# are the data signals. DBR# is not a processor signal. Signal Description (Sheet 3 of the data signals. DBR# is ...
... active, the corresponding data group is a no debug port is in use. If a debug port is implemented in the system. The data driver asserts DRDY# to a pair of the D[63:0]# signals.The DBI[3:0]# signals are source synchronous and indicate the polarity of one DSTBP# and ... determine the polarity of 9) Name Type Description D[63:0]# (Data) are quad-pumped signals and will, thus, be driven four times in -target probe can drive system reset. D[63:0]# are the data signals. DBR# is not a processor signal. Signal Description (Sheet 3 of the data signals. DBR# is ...
Data Sheet
Page 65
...-asserted to volume 3 of 9) Name DEFER# DRDY# Type Description Input DEFER# is asserted by the data driver on each data transfer, indicating valid data on the Intel 387 coprocessor, and is asserted, an assertion of all processor FSB agents. Signals Associated Strobe DSTBN[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2...
...-asserted to volume 3 of 9) Name DEFER# DRDY# Type Description Input DEFER# is asserted by the data driver on each data transfer, indicating valid data on the Intel 387 coprocessor, and is asserted, an assertion of all processor FSB agents. Signals Associated Strobe DSTBN[3:0]# Input/ Output D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2...
Data Sheet
Page 77
...and voltage. Refer to prevent rapid active/inactive transitions of 5 μs). Datasheet 77 The TCC causes the processor to service any additional hardware, software drivers, or interrupt handling routines. These parameters represent normal system operation. Each step will occur first, in the ... be activated. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the lower voltage reduces the power consumption of this condition, the core-frequency-to reach the target operating voltage. Once the temperature has dropped below ...
...and voltage. Refer to prevent rapid active/inactive transitions of 5 μs). Datasheet 77 The TCC causes the processor to service any additional hardware, software drivers, or interrupt handling routines. These parameters represent normal system operation. Each step will occur first, in the ... be activated. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the lower voltage reduces the power consumption of this condition, the core-frequency-to reach the target operating voltage. Once the temperature has dropped below ...